Considerations for Ultimate CMOS Scaling

This review paper explores considerations for ultimate CMOS transistor scaling. Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted. Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results.

[1]  Hyung-Kyu Lim,et al.  Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's , 1983, IEEE Transactions on Electron Devices.

[2]  T. Sekigawa,et al.  Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate , 1984 .

[3]  J. Colinge.  Transconductance of Silicon-on-insulator (SOI) MOSFET's , 1985, IEEE Electron Device Letters.

[4]  J. Colinge.  Subthreshold slope of thin-film SOI MOSFET's , 1986, IEEE Electron Device Letters.

[5]  F. Balestra,et al.  Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance , 1987, IEEE Electron Device Letters.

[6]  Y. Tsividis.  Operation and modeling of the MOS transistor , 1987 .

[7]  J. Colinge.  Reduction of kink effect in thin-film SOI MOSFETs , 1988, IEEE Electron Device Letters.

[8]  D. Hisamoto,et al.  A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET , 1989, International Technical Digest on Electron Devices Meeting.

[9]  J. Colinge,et al.  Silicon-on-insulator 'gate-all-around device' , 1990, International Technical Digest on Electron Devices.

[10]  D. Hisamoto,et al.  A fully depleted lean-channel transistor (DELTA)-a novel vertical ultrathin SOI MOSFET , 1990, IEEE Electron Device Letters.

[11]  Fumio Horiguchi,et al.  Impact of surrounding gate transistor (SGT) for ultra-high-density LSI's , 1991 .

[12]  D. Hisamoto,et al.  Impact of the vertical SOI 'DELTA' structure on planar device technology , 1991 .

[13]  J. Welser,et al.  NMOS and PMOS transistors fabricated in strained silicon/relaxed silicon-germanium structures , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[14]  S. S. Yuen,et al.  Recess channel structure for reducing source/drain series resistance in ultra-thin SOI MOSFETs , 1993, Proceedings of 1993 IEEE International SOI Conference.

[15]  J. Welser,et al.  Strain dependence of the performance enhancement in strained-Si n-MOSFETs , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[16]  J. Welser,et al.  Enhanced hole mobilities in surface-channel strained-Si p-MOSFETs , 1995, Proceedings of International Electron Devices Meeting.

[17]  R. Opila,et al.  In-situ Ga/sub 2/O/sub 3/ process for GaAs inversion/accumulation device and surface passivation applications , 1995, Proceedings of International Electron Devices Meeting.

[18]  D. Antoniadis,et al.  Channel profile engineering for MOSFET's with 100 nm channel lengths , 1995 .

[19]  C. Hu,et al.  A comparative study of advanced MOSFET concepts , 1996 .

[20]  M. Passlack,et al.  Quasistatic and high frequency capacitance–voltage characterization of Ga2O3–GaAs structures fabricated by in situ molecular beam epitaxy , 1996 .

[21]  J. Kwo,et al.  Recombination velocity at oxide–GaAs interfaces fabricated by in situ molecular beam epitaxy , 1996 .

[22]  H.-S.P. Wong,et al.  Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[23]  Bin Yu,et al.  Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET's , 1997 .

[24]  Chenming Hu,et al.  A folded-channel MOSFET for deep-sub-tenth micron era , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[25]  S. Thompson.  MOS Scaling: Transistor Challenges for the 21st Century , 1998 .

[26]  W. Lai,et al.  The Vertical Replacement-Gate (VRG) MOSFET: a 50-nm vertical MOSFET with lithography-independent gate length , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[27]  Jong-Ho Lee,et al.  Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[28]  Chenming Hu,et al.  Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[29]  K. Rim,et al.  Fabrication and analysis of deep submicron strained-Si n-MOSFET's , 2000 .

[30]  K. Yamaguchi,et al.  Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[31]  Chenming Hu,et al.  Ultrathin-body SOI MOSFET for deep-sub-tenth micron era , 2000, IEEE Electron Device Letters.

[32]  J. Treichler,et al.  Triple-self-aligned, planar double-gate MOSFETs: devices and circuits , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[33]  E. Nowak,et al.  High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[34]  Jong-Tea Park,et al.  Pi-Gate SOI MOSFET , 2001, IEEE Electron Device Letters.

[35]  A. Grill,et al.  Strained Si NMOSFETs for high performance CMOS technology , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

[36]  K. Matsuzawa,et al.  SiGe source/drain structure for the suppression of the short-channel effect of sub-0.1-/spl mu/m p-channel MOSFETs , 2001 .

[37]  E. Cartier,et al.  Effective electron mobility in Si inversion layers in metal–oxide–semiconductor systems with a high-κ insulator: The role of remote phonon scattering , 2001 .

[38]  James D. Plummer,et al.  Material and process limits in silicon VLSI technology , 2001, Proc. IEEE.

[39]  J. Woo,et al.  Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS , 2002 .

[40]  H. Nayfeh,et al.  Strained silicon MOSFET technology , 2002, Digest. International Electron Devices Meeting,.

[41]  P. Bai,et al.  A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell , 2002, Digest. International Electron Devices Meeting,.

[42]  Y. Yeo,et al.  25 nm CMOS Omega FETs , 2002, Digest. International Electron Devices Meeting,.

[43]  T. Skotnicki,et al.  50 nm-Gate All Around (GAA)-Silicon On Nothing (SON)-devices: a simple way to co-integration of GAA transistors within bulk MOSFET process , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[44]  T. Eimori,et al.  Novel locally strained channel technique for high performance 55nm CMOS , 2002, Digest. International Electron Devices Meeting,.

[45]  M. Ieong,et al.  Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[46]  J. Kavalieros,et al.  High performance fully-depleted tri-gate CMOS transistors , 2003, IEEE Electron Device Letters.

[47]  General review of issues and perspectives for advanced copper interconnections using air gap as ultra-low K material , 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).

[48]  M. Silberstein,et al.  A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors , 2003, IEEE International Electron Devices Meeting 2003.

[49]  J. Kwo,et al.  GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition , 2003, IEEE Electron Device Letters.

[50]  S. Hareland,et al.  Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

[51]  Y. Yeo,et al.  Enhanced performance in 50 nm N-MOSFETs with silicon-carbon source/drain regions , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[52]  R. Chau,et al.  A 90-nm logic technology featuring strained-silicon , 2004, IEEE Transactions on Electron Devices.

[53]  T. Ghani,et al.  Front end stress modeling for advanced logic technologies , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[54]  S. Borkar,et al.  Circuit techniques for subthreshold leakage avoidance, control and tolerance , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[55]  C.C. Chen,et al.  Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[56]  R. Kotlyar,et al.  Understanding stress enhanced performance in Intel 90nm CMOS technology , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[57]  S. Satoh,et al.  A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[58]  S. Thompson,et al.  Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[59]  R. Kotlyar,et al.  Assessment of room-temperature phonon-limited mobility in gated silicon nanowires , 2004 .

[60]  K. Saraswat,et al.  Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[61]  T. Tezuka,et al.  A new strained-SOI/GOI dual CMOS technology based on local condensation technique , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[62]  B. Ryu,et al.  High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[63]  Avik W. Ghosh,et al.  Theoretical investigation of surface roughness scattering in silicon nanowire transistors , 2005, cond-mat/0502538.

[64]  Anna W. Topol,et al.  High performance FDSOI CMOS technology with metal gate and high-k , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[65]  Changhwan Choi,et al.  Fabrication of TaN-gated ultra-thin MOSFETs (EOT <1.0 nm) with HfO/sub 2/ using a novel oxygen scavenging process for sub 65 nm application , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[66]  K. Saraswat,et al.  Low defect ultra-thin fully strained-Ge MOSFET on relaxed Si with high mobility and low band-to-band-tunneling (BTBT) , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[67]  N. Cherkashin,et al.  Strained Si and Ge MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[68]  C. O. Chui,et al.  High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs , 2006, 2006 International Electron Devices Meeting.

[69]  B. Ryu,et al.  Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires , 2006, 2006 International Electron Devices Meeting.

[70]  Hyungcheol Shin,et al.  The Air Spacer Technology for Improving the Cell Distribution in 1 Giga Bit NAND Flash Memory , 2006, 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop.

[71]  G. Dewey,et al.  Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[72]  S. Selberherr,et al.  Theoretical Investigation Of Performance In Uniaxially- and Biaxially-Strained Si, SiGe and Ge Double-Gate p-MOSFETs , 2006, 2006 International Electron Devices Meeting.

[73]  A. Toffoli,et al.  Ultra-Thin Fully Depleted SOI Devices with Thin BOX, Ground Plane and Strained Liner Booster , 2006, 2006 IEEE international SOI Conferencee Proceedings.

[74]  O. Faynot,et al.  25nm Short and Narrow Strained FDSOI with TiN/HfO2 Gate Stack , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[75]  T. Adam,et al.  Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain , 2006, 2009 Symposium on VLSI Technology.

[76]  S. Suk,et al.  Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate , 2006, 2009 Symposium on VLSI Technology.

[77]  A. Stesmans,et al.  Impact of EOT scaling down to 0.85nm on 70nm Ge-pFETs technology with STI , 2006, 2009 Symposium on VLSI Technology.

[78]  M. Ieong,et al.  Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[79]  J. Larson,et al.  Overview and status of metal S/D Schottky-barrier MOSFET technology , 2006, IEEE Transactions on Electron Devices.

[80]  P. Ye,et al.  Capacitance-voltage studies on enhancement-mode InGaAs metal-oxide-semiconductor field-effect transistor using atomic-layer-deposited Al2O3 gate dielectric , 2006 .

[81]  K. Opsomer,et al.  High performance Ge pMOS devices using a Si-compatible process flow , 2006, 2006 International Electron Devices Meeting.

[82]  M. Gerhardt,et al.  Multiple Stress Memorization In Advanced SOI CMOS Technologies , 2007, 2007 IEEE Symposium on VLSI Technology.

[83]  O. Weber,et al.  Examination of Additive Mobility Enhancements for Uniaxial Stress Combined with Biaxially Strained Si, Biaxially Strained SiGe and Ge Channel MOSFETs , 2007, 2007 IEEE International Electron Devices Meeting.

[84]  A. Lochtefeld,et al.  Inversion-type enhancement-mode InP MOSFETs with ALD Al2O3, HfO2 and HfAlO nanolaminates as high-k gate dielectrics , 2007, 2007 65th Annual Device Research Conference.

[85]  C. Lavoie,et al.  Strained Si Channel MOSFETs with Embedded Silicon Carbon Formed by Solid Phase Epitaxy , 2007, 2007 IEEE Symposium on VLSI Technology.

[86]  K. Saraswat,et al.  Interface-Engineered Ge (100) and (111), N- and P-FETs with High Mobility , 2007, 2007 IEEE International Electron Devices Meeting.

[87]  R. Chau,et al.  A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging , 2007, 2007 IEEE International Electron Devices Meeting.

[88]  Shi-Li Zhang,et al.  Schottky-Barrier Height Tuning by Means of Ion Implantation Into Preformed Silicide Films Followed by Drive-In Anneal , 2007, IEEE Electron Device Letters.

[89]  Y. Tagawa,et al.  Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates , 2007, 2007 IEEE International Electron Devices Meeting.

[90]  M. Fischetti,et al.  Modeling of electron mobility in gated silicon nanowires at room temperature: Surface roughness scattering, dielectric screening, and band nonparabolicity , 2007 .

[91]  O. Faynot,et al.  Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2 gate stack , 2007, 2007 IEEE International Electron Devices Meeting.

[92]  J. Koga,et al.  Interfacial Segregation of Metal at NiSi/Si Junction for Novel Dual Silicide Technology , 2007, 2007 IEEE International Electron Devices Meeting.

[93]  Y. Tagawa,et al.  Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process , 2007, 2007 IEEE Symposium on VLSI Technology.

[94]  Marvin L. Cohen,et al.  Possibility of increased mobility in Ge-Sn alloy system , 2007 .

[95]  G. Ghibaudo,et al.  Localized ultra-thin GeOI: An innovative approach to germanium channel MOSFETs on bulk Si substrates , 2008, 2008 IEEE International Electron Devices Meeting.

[96]  W. Lee,et al.  A novel CVD-SiBCN Low-K spacer technology for high-speed applications , 2008, 2008 Symposium on VLSI Technology.

[97]  R. Loo,et al.  Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability , 2008, 2008 IEEE International Electron Devices Meeting.

[98]  O. Faynot,et al.  15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET , 2008, 2008 IEEE International Electron Devices Meeting.

[99]  T. Adam,et al.  On implementation of embedded phosphorus-doped SiC stressors in SOI nMOSFETs , 2008, 2008 Symposium on VLSI Technology.

[100]  C. Auth,et al.  45nm High-k + metal gate strain-enhanced transistors , 2008, 2008 Symposium on VLSI Technology.

[101]  Mark Y. Liu,et al.  A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array , 2008, 2008 IEEE International Electron Devices Meeting.

[102]  T. Ma,et al.  Properties of InAs metal-oxide-semiconductor structures with atomic-layer-deposited Al2O3 Dielectric , 2008 .

[103]  K. Saraswat,et al.  Comparison of (001), (110) and (111) uniaxial- and biaxial- strained-Ge and strained-Si PMOS DGFETs for all channel orientations: Mobility enhancement, drive current, delay and off-state leakage , 2008, 2008 IEEE International Electron Devices Meeting.

[104]  T. Schram,et al.  Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay , 2008, 2008 Symposium on VLSI Technology.

[105]  R. Kotlyar,et al.  High performance Hi-K + metal gate strain enhanced transistors on (110) silicon , 2008, 2008 IEEE International Electron Devices Meeting.

[106]  G. Dewey,et al.  High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC=0.5V) logic applications , 2008, 2008 IEEE International Electron Devices Meeting.

[107]  Chunxiang Zhu,et al.  High mobility high-k/Ge pMOSFETs with 1 nm EOT -New concept on interface engineering and interface characterization , 2008, 2008 IEEE International Electron Devices Meeting.

[108]  Gerhard Klimeck,et al.  Bandstructure Effects in Silicon Nanowire Electron Transport , 2007, IEEE Transactions on Electron Devices.

[109]  C. Merckling,et al.  Germanium for advanced CMOS anno 2009: a SWOT analysis , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[110]  R. Kotlyar,et al.  Modeling the effects of applied stress and wafer orientation in silicon devices: from long channel mobility physics to short channel performance , 2009 .

[111]  K. Saraswat,et al.  Experimental demonstration of high mobility Ge NMOS , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[112]  N. Collaert,et al.  Review of FINFET technology , 2009, 2009 IEEE International SOI Conference.

[113]  T. Vandeweyer,et al.  High Performance 70-nm Germanium pMOSFETs With Boron LDD Implants , 2009, IEEE Electron Device Letters.

[114]  S. Shue,et al.  Low capacitance approaches for 22nm generation Cu interconnect , 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

[115]  K. Maitra,et al.  Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[116]  D. Antoniadis,et al.  Extraction of virtual-source injection velocity in sub-100 nm III–V HFETs , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[117]  C. H. Lee,et al.  Record-high electron mobility in Ge n-MOSFETs exceeding Si universality , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[118]  P. Ye,et al.  Inversion-Mode Inxga1-Xas Mosfets (X=0.53,0.65,0.75) with Atomic-Layerdeposited High-K Dielectrics , 2009 .

[119]  C. Hu,et al.  Air-Spacer MOSFET With Self-Aligned Contact for Future Dense Memories , 2009, IEEE Electron Device Letters.

[120]  K. Saraswat,et al.  Ge (100) and (111) N- and P-FETs With High Mobility and Low- $T$ Mobility Characterization , 2009, IEEE Transactions on Electron Devices.

[121]  C. H. Lee,et al.  Comprehensive study of GeO2 oxidation, GeO desorption and GeO2-metal interaction -understanding of Ge processing kinetics for perfect interface control- , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[122]  H. Huff.  Into The Nano Era , 2009 .

[123]  J. Liaw,et al.  A 25-nm gate-length FinFET transistor module for 32nm node , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[124]  G. Dewey,et al.  Advanced high-K gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[125]  G. Cohen,et al.  High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[126]  J. Alamo.  Quantum capacitance in scaled down III-V FETs , 2009 .

[127]  S. Stemmer,et al.  Metal-oxide-semiconductor capacitors with ZrO2 dielectrics grown on In0.53Ga0.47As by chemical beam deposition , 2009 .

[128]  J. Jopling,et al.  High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[129]  L. H. Vanamurth,et al.  Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[130]  Y. Kamata,et al.  High-k/Ge p- & n-MISFETs with strontium germanide interlayer for EOT scalable CMIS application , 2010, 2010 Symposium on VLSI Technology.

[131]  G. Dewey,et al.  Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications , 2010, 2010 International Electron Devices Meeting.

[132]  C. Carabasse,et al.  Experimental study on carrier transport limiting phenomena in 10 nm width nanowire CMOS transistors , 2010, 2010 International Electron Devices Meeting.

[133]  F. Zahid,et al.  Resistivity of thin Cu films coated with Ta, Ti, Ru, Al, and Pd barrier layers from first principles , 2010 .

[134]  M. Passlack,et al.  Suitability Study of Oxide/Gallium Arsenide Interfaces for MOSFET Applications , 2010, IEEE Transactions on Electron Devices.

[135]  T. Boykin,et al.  III–V FET channel designs for high current densities and thin inversion layers , 2010, 68th Device Research Conference.

[136]  Weichao Wang,et al.  Impact of Interfacial Oxygen Content on Bonding, Stability, Band Offsets, and Interface States of GaAs:HfO2 Interfaces , 2010 .

[137]  O. Weber,et al.  Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond , 2010, 2010 International Electron Devices Meeting.

[138]  T. Skotnicki,et al.  How can high mobility channel materials boost or degrade performance in advanced CMOS , 2010, 2010 Symposium on VLSI Technology.

[139]  P. Ye,et al.  Heteroepitaxy of single-crystal LaLuO3 on GaAs(111)A by atomic layer deposition , 2010 .

[140]  A. Toffoli,et al.  Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond , 2010, 2010 Symposium on VLSI Technology.

[141]  C. Chung,et al.  Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices , 2010, 2010 International Electron Devices Meeting.

[142]  J. Rizk,et al.  RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications , 2010, 2010 International Electron Devices Meeting.

[143]  K. Nagashio,et al.  Desorption kinetics of GeO from GeO2/Ge structure , 2010 .

[144]  G. Dewey,et al.  High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture , 2010, 2010 International Electron Devices Meeting.

[145]  Kelin J. Kuhn,et al.  (Invited) Past, Present and Future: SiGe and CMOS Transistor Scaling , 2010, ECS Transactions.

[146]  Min Cao,et al.  A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology , 2010, 2010 International Electron Devices Meeting.

[147]  L. Gomez,et al.  Enhanced Hole Mobility in High Ge Content Asymmetrically Strained-SiGe p-MOSFETs , 2010, IEEE Electron Device Letters.

[148]  C. Merckling,et al.  High FET Performance for a Future CMOS $\hbox{GeO}_{2}$ -Based Technology , 2010, IEEE Electron Device Letters.

[149]  H. Sunamura,et al.  Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond , 2010, 2010 Symposium on VLSI Technology.

[150]  E. Joseph,et al.  Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm , 2010, 2010 Symposium on VLSI Technology.

[151]  J. H. Chen,et al.  High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme , 2010, 2010 International Electron Devices Meeting.

[152]  P. Kirsch,et al.  Strained SiGe and Si FinFETs for high performance logic with SiGe/Si stack on SOI , 2010, 2010 International Electron Devices Meeting.

[153]  R. Wallace,et al.  Contact Resistance Reduction to FinFET Source/Drain Using Novel Dielectric Dipole Schottky Barrier Height Modulation Method , 2011, IEEE Electron Device Letters.

[154]  K. Tabakman,et al.  Assessment of fully-depleted planar CMOS for low power complex circuit operation , 2011, 2011 International Electron Devices Meeting.

[155]  M. D. Giles,et al.  Process Technology Variation , 2011, IEEE Transactions on Electron Devices.

[156]  S. Narasimha,et al.  A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications , 2011, 2011 International Electron Devices Meeting.

[157]  J. Robertson,et al.  Defect states at III-V semiconductor oxide interfaces , 2011 .

[158]  L. Xia,et al.  Performance enhancement of p-channel InGaAs quantum-well FETs by superposition of process-induced uniaxial strain and epitaxially-grown biaxial strain , 2011, 2011 International Electron Devices Meeting.

[159]  Y. Yeo,et al.  High-mobility germanium-tin (GeSn) P-channel MOSFETs featuring metallic source/drain and sub-370 °C process modules , 2011, 2011 International Electron Devices Meeting.

[160]  J. Shepard,et al.  A novel atomic layer oxidation technique for EOT scaling in gate-last high-к/metal gate CMOS technology , 2011, 2011 International Electron Devices Meeting.

[161]  Mark Y. Liu,et al.  Modeling of NMOS performance gains from edge dislocation stress , 2011, 2011 International Electron Devices Meeting.

[162]  A. Hikavyy,et al.  High performance Si.45Ge.55 Implant Free Quantum Well FET featuring low temperature process, eSiGe stressor and transversal strain relaxation , 2011, 2011 International Electron Devices Meeting.

[163]  Mark Bohr,et al.  The evolution of scaling from the homogeneous era to the heterogeneous era , 2011, 2011 International Electron Devices Meeting.

[164]  M. Caymax,et al.  Atomic layer deposition of Al2O3 on S-passivated Ge , 2011 .

[165]  A. Hikavyy,et al.  Advancing CMOS beyond the Si roadmap with Ge and III/V devices , 2011, 2011 International Electron Devices Meeting.

[166]  A. Kellock,et al.  Maximized Benefit of La–Al–O Higher-$k$ Gate Dielectrics by Optimizing the La/Al Atomic Ratio , 2011, IEEE Electron Device Letters.

[167]  Isabelle Ferain,et al.  Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors , 2011, Nature.

[168]  Chi-Woo Lee,et al.  Quantum Confinement Effects in Capacitance Behavior of Multigate Silicon Nanowire MOSFETs , 2011, IEEE Transactions on Nanotechnology.

[169]  T. Fukui,et al.  Vertical In0.7Ga0.3As nanowire surrounding-gate transistors with high-k gate dielectric on Si substrate , 2011, 2011 International Electron Devices Meeting.

[170]  O. Faynot,et al.  First demonstration of ultrathin body c-SiGe channel FDSOI pMOSFETs combined with SiGe(:B) RSD: Drastic improvement of electrostatics (Vth,p tuning, DIBL) and transport (μ0, Isat) properties down to 23nm gate length , 2011, 2011 International Electron Devices Meeting.

[171]  T. Adam,et al.  ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[172]  C. H. Lee,et al.  Material potential and scalability challenges of germanium CMOS , 2011, 2011 International Electron Devices Meeting.

[173]  K. Saraswat,et al.  GeSn technology: Extending the Ge electronics roadmap , 2011, 2011 International Electron Devices Meeting.

[174]  A. Hikavyy,et al.  1mA/um-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[175]  J. D. del Alamo.  Nanometre-scale electronics with III-V compound semiconductors. , 2011, Nature.

[176]  R. Kotlyar,et al.  Effects of Surface Orientation on the Performance of Idealized III–V Thin-Body Ballistic n-MOSFETs , 2011, IEEE Electron Device Letters.

[177]  S. Choi,et al.  Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications , 2011, 2011 International Electron Devices Meeting.

[178]  B. Douhard,et al.  High performance n-MOS finFET by damage-free, conformal extension doping , 2011, 2011 International Electron Devices Meeting.

[179]  N. Taoka,et al.  High mobility Ge pMOSFETs with ∼ 1nm thin EOT using Al2O3/GeOx/Ge gate stacks fabricated by plasma post oxidation , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[180]  G. Bersuker,et al.  300mm FinFET results utilizing conformal, damage free, ultra shallow junctions (Xj∼5nm) formed with molecular monolayer doping technique , 2011, 2011 International Electron Devices Meeting.

[181]  M. Belleville,et al.  Drain current variability and MOSFET parameters correlations in planar FDSOI technology , 2011, 2011 International Electron Devices Meeting.

[182]  A. Hikavyy,et al.  Dual-channel technology with cap-free single metal gate for high performance CMOS in gate-first and gate-last integration , 2011, 2011 International Electron Devices Meeting.

[183]  N. Taoka,et al.  Enhancement technologies and physical understanding of electron mobility in III–V n-MOSFETs with strain and MOS interface buffer engineering , 2011, 2011 International Electron Devices Meeting.

[184]  G. Dewey,et al.  Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation , 2011, 2011 International Electron Devices Meeting.

[185]  N. Taoka,et al.  1-nm-thick EOT high mobility Ge n- and p-MOSFETs with ultrathin GeOx/Ge MOS interfaces fabricated by plasma post oxidation , 2011, 2011 International Electron Devices Meeting.

[186]  H. Ryu,et al.  Ohm’s Law Survives to the Atomic Scale , 2012, Science.

[187]  C. Auth,et al.  A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[188]  R. Kotlyar,et al.  Does the Low Hole Transport Mass in and Si Nanowires Lead to Mobility Enhancements at High Field and Stress: A Self-Consistent Tight-Binding Study , 2012 .