论文信息 - CMOS-photonic “macrochip” packaging

CMOS-photonic “macrochip” packaging

Two novel packaging technologies have been developed to serve as essential building blocks for construction of a photonically interconnected large-chip array. Ultralow parasitic microsolder interconnections (on the order of 100 mOhm/bump and 25 fF/bump) allow combination of best-in-class chips, which may be built on different technology platforms, and CMOS compatible ball-in-etch-pit structures provide a non-permanent passive selfaligning mechanism for highly accurate componentto-component placement.

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