A Simple and Reliable System to Detect and Correct Setup/Hold Time Violations in Digital Circuits

In this article, a fully digital system to detect and correct setup/hold time violations in digital circuits, is presented. The proposed system benefits from simple, low-power, small-area, and easy-to-modify design. The system is composed of two separate blocks, detector and corrector connected through a 2-bit control signal. The detector is placed near flip-flops or memory elements and sends control signals to the corrector. Corrector circuitry consists of only CMOS inverters and a multiplexer, either after global clock source to correct clock globally or before the elements to correct them locally. Because of its simplicity, this system can be repeatedly used throughout the chip. Also it is proved that the correction circuitry may be realized by employing only a few CMOS inverters without any need for adjusting the delay of the inverters. Furthermore, mathematical proof for the ability of the inverter-based correction circuitry is provided. The system continuously monitors and corrects any setup/hold time violations up to the highest possible operating frequency a given process allows.

[1]  Masanori Hashimoto,et al.  Timing analysis considering temporal supply voltage fluctuation , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[2]  Grigor Y. Zargaryan,et al.  Data — Clock setup and hold times margins correction method in high speed serial links , 2013, Ninth International Conference on Computer Science and Information Technologies Revised Selected Papers.

[3]  Taewhan Kim,et al.  An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Kunihiro Asada,et al.  A circuit for on-chip skew adjustment with jitter and setup time measurement , 2010, 2010 IEEE Asian Solid-State Circuits Conference.

[5]  Chi-Chou Kao,et al.  Clock skew minimization with adjustable delay buffers restriction , 2013, 2013 International Symposium on Next-Generation Electronics.

[6]  Kwanyeob Chae,et al.  A Dynamic Timing Error Prevention Technique in Pipelines With Time Borrowing and Clock Stretching , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Masanori Hashimoto,et al.  Setup time, hold time and clock-to-Q delay computation under dynamic supply noise , 2010, IEEE Custom Integrated Circuits Conference 2010.

[8]  Wing-Kai Hon,et al.  Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Shih-Hsu Huang,et al.  PVT-variations-tolerant clock design using self-correcting adjustable delay buffers , 2014, 2014 International Symposium on Next-Generation Electronics (ISNE).