Multiple fault diagnosis using n-detection tests

We study the relationship between multiple fault diagnosability and fault detection count. Instead of developing a complex diagnostic algorithm for multiple fault behavior, we change the test sets used in test and diagnosis. This allows us to apply a simple single-fault based diagnostic algorithm, and yet achieve very good diagnosability for the failure test cases caused by multiple faults. We have verified experimentally the effectiveness of n-detection tests for multiple-fault cases and explained the results in probabilistic terms.

[1]  J.A. Waicukauski,et al.  Failure diagnosis of structured VLSI , 1989, IEEE Design & Test of Computers.

[2]  Janusz Rajski,et al.  Impact of multiple-detect test patterns on product quality , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[3]  Irith Pomeranz,et al.  On the use of fault dominance in n-detection test generation , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[4]  Barry K. Rosen,et al.  Comparison of AC Self-Testing Procedures , 1983, ITC.

[5]  Edward J. McCluskey,et al.  Stuck-fault tests vs. actual defects , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[6]  M. Ray Mercer,et al.  A new ATPG algorithm to limit test set size and achieve multiple detections of all faults , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[7]  Irith Pomeranz,et al.  Exact computation of maximally dominating faults and its application to n-detection tests , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

[8]  Nilanjan Mukherjee,et al.  Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.

[9]  Malgorzata Marek-Sadowska,et al.  An efficient and effective methodology on the multiple fault diagnosis , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[10]  Venkatram Krishnaswamy,et al.  A study of bridging defect probabilities on a Pentium (TM) 4 CPU , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[11]  Irith Pomeranz,et al.  Compact test sets for high defect coverage , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .