Ultralow-Power Single-Wall Carbon Nanotube Interconnects for Subthreshold Circuits

Single-wall carbon nanotube (SWNT) interconnects, though seem promising, have fundamental and practical limitations. The resistance of individual SWNTs is quite large because of which dense SWNT bundles are needed. However, there has been little progress in wafer-level fabrication of horizontal bundles of densely packed nanotubes. This letter reports that individual SWNTs can be used as interconnects in subthreshold circuits to improve delay and energy-per-bit by up to 5 times and 6 times, respectively. In light of recent advances in wafer-level fabrication of long aligned isolated SWNTs, the presented results can potentially open up a new and less challenging path toward SWNT interconnects.

[1]  A. Wang,et al.  Modeling and sizing for minimum energy operation in subthreshold circuits , 2005, IEEE Journal of Solid-State Circuits.

[2]  Naveen Verma,et al.  12.5 A 25µW 100kS/s 12b ADC for Wireless Micro-Sensor Applications , 2006 .

[3]  Kaushik Roy,et al.  Ultra-low power DLMS adaptive filter for hearing aid applications , 2001, ISLPED '01.

[4]  Takeo Yamada,et al.  84% catalyst activity of water-assisted growth of single walled carbon nanotube forest characterization by a statistical and macroscopic approach. , 2006, The journal of physical chemistry. B.

[5]  Michael D. Godfrey CMOS device modeling for subthreshold circuits , 1992 .

[6]  P. Ajayan,et al.  Highly aligned scalable platinum-decorated single-wall carbon nanotube arrays for nanoscale electrical interconnects. , 2009, ACS nano.

[7]  P. Burke,et al.  An RF circuit model for carbon nanotubes , 2002, Proceedings of the 2nd IEEE Conference on Nanotechnology.

[8]  A.P. Chandrakasan,et al.  A 25/spl mu/W 100kS/s 12b ADC for wireless micro-sensor applications , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[9]  Shyh-Chyi Wong,et al.  Modeling of interconnect capacitance, delay, and crosstalk in VLSI , 2000 .

[10]  P. Kapur,et al.  Performance Comparisons Between Carbon Nanotubes, Optical, and Cu for Future High-Performance On-Chip Interconnect Applications , 2007, IEEE Transactions on Electron Devices.

[11]  Alan C. Thomas,et al.  Level-specific lithography optimization for 1-Gb DRAM , 2000 .

[12]  Subhasish Mitra,et al.  CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes. , 2009, Nano letters.

[13]  Y. Massoud,et al.  Evaluating the impact of resistance in carbon nanotube bundles for VLSI interconnect using diameter-dependent modeling techniques , 2006, IEEE Transactions on Electron Devices.

[14]  Makoto Kanda,et al.  Large-scale separation of metallic and semiconducting single-walled carbon nanotubes. , 2005, Journal of the American Chemical Society.

[15]  K. Roy,et al.  Double gate-MOSFET subthreshold circuit for ultralow power applications , 2004, IEEE Transactions on Electron Devices.

[16]  James D. Meindl,et al.  Carbon nanotube interconnects , 2007, ISPD '07.