Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking—Part I: Constant Input
暂无分享,去创建一个
[1] M. A. Copeland,et al. Design and realization of a digital /spl Delta//spl Sigma/ modulator for fractional-n frequency synthesis , 1999 .
[2] Juha Kostamovaara,et al. A practical Δ-Σ modulator design method based on periodical behavior analysis. , 2005 .
[3] Juha Kostamovaara,et al. A practical /spl Delta/-/spl Sigma/ modulator design method based on periodical behavior analysis , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.
[4] I. Fujimori,et al. A multibit delta-sigma audio DAC with 120-dB dynamic range , 2000, IEEE Journal of Solid-State Circuits.
[5] K. Hosseini,et al. Mathematical analysis of digital MASH delta-sigma modulators for fractional-N frequency synthesizers , 2006, 2006 Ph.D. Research in Microelectronics and Electronics.
[6] Michael Peter Kennedy,et al. Prediction of the Spectrum of a Digital Delta–Sigma Modulator Followed by a Polynomial Nonlinearity , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.
[7] Pin-En Su,et al. Fractional-$N$ Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.
[8] Michael Peter Kennedy,et al. Mathematical Analysis of a Prime Modulus Quantizer MASH Digital Delta–Sigma Modulator , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.
[9] Alan V. Oppenheim,et al. Discrete-Time Signal Pro-cessing , 1989 .
[10] Bob Adams,et al. A 108dB SNR 1.1mW Oversampling Audio DAC with a Three-Level DEM Technique , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[11] R. Castello,et al. A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications , 2004, IEEE Journal of Solid-State Circuits.
[12] Chih-Kong Ken Yang,et al. A 14-bit, 10-Msamples/s D/A converter using multibit /spl Sigma//spl Delta/ modulation , 1999 .
[13] Andrea Baschirotto,et al. Behavioral modeling of switched-capacitor sigma-delta modulators , 2003 .
[14] Zhipeng Ye,et al. Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part I: MASH DDSM , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.
[15] Michael Peter Kennedy,et al. Maximum Sequence Length MASH Digital Delta–Sigma Modulators , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.
[16] Franco Maloberti,et al. Efficient Dithering in MASH Sigma-Delta Modulators for Fractional Frequency Synthesizers , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.
[17] Michael Peter Kennedy,et al. Architectures for Maximum-Sequence-Length Digital Delta-Sigma Modulators , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.
[18] Michael Peter Kennedy,et al. A novel implementation of dithered digital delta-sigma modulators via bus-splitting , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).
[19] Atsushi Iwata,et al. Oversampling A-to-D and D-to-A converters with multistage noise shaping modulators , 1988, IEEE Trans. Acoust. Speech Signal Process..
[20] Dandan Li,et al. Stable high-order delta-sigma digital-to-analog converters , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.
[21] In-Cheol Park,et al. Spur-Free MASH Delta-Sigma Modulation , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.
[22] A. Baschirotto,et al. A 0.22-mm/sup 2/ 7.25-mW per-channel audio stereo-DAC with 97-dB DR and 39-dB SNR/sub out/ , 2005, IEEE Journal of Solid-State Circuits.
[23] Michael Peter Kennedy,et al. A nested digital delta-sigma modulator architecture for fractional-N frequency synthesis , 2010, 6th Conference on Ph.D. Research in Microelectronics & Electronics.
[24] Chia-Yu Yao,et al. Hardware Simplification to the Delta Path in a MASH 111 Delta–Sigma Modulator , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.
[25] Sudhakar Pamarti,et al. LSB Dithering in MASH Delta–Sigma D/A Converters , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.
[26] Chi-Ying Tsui,et al. IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.
[27] D. A. Rich,et al. A minimal multibit digital noise shaping architecture , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.
[28] M. A. Copeland,et al. Design and realization of a digital ??? modulator for fractional-n frequency synthesis , 1999 .
[29] Andrea Baschirotto,et al. A low-power 98-dB multibit audio DAC in a standard 3.3-V 0.35-/spl mu/m CMOS technology , 2002 .
[30] Ian Galton,et al. Granular quantization noise in the first-order delta-sigma modulator , 1993, IEEE Trans. Inf. Theory.
[31] K. Hosseini,et al. Calculation of sequence lengths in MASH 1-1-1 digital delta sigma modulators with a constant input , 2007, 2007 Ph.D Research in Microelectronics and Electronics Conference.
[32] Izzet Kale,et al. A pipelined noise shaping coder for fractional-N frequency synthesis , 2001, IEEE Trans. Instrum. Meas..
[33] K. Nguyen,et al. A 108 dB SNR, 1.1 mW Oversampling Audio DAC With A Three-level DEM Technique , 2008, IEEE Journal of Solid-State Circuits.
[34] Sudhakar Pamarti,et al. Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta–Sigma Modulators , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.
[35] Zhipeng Ye,et al. Hardware Reduction in Digital Delta–Sigma Modulators Via Error Masking—Part II: SQ-DDSM , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.
[36] Ian Galton. One-bit dithering in delta-sigma modulator-based D/A conversion , 1993, 1993 IEEE International Symposium on Circuits and Systems.
[37] James C. Candy,et al. Double Interpolation for Digital-to-Analog Conversion , 1986, IEEE Trans. Commun..
[38] Mohammed Ismail,et al. Multimode Reconfigurable Digital $\Sigma\Delta$ Modulator Architecture for Fractional-$N$ PLLs , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.
[39] Ali Afzali-Kusha,et al. Reduced complexity 1-bit high-order digital delta-sigma modulator for low-voltage fractional-N frequency synthesis applications , 2005 .
[40] Wu Chou,et al. Dithering and its effects on sigma-delta and multistage sigma-delta modulation , 1991, IEEE Trans. Inf. Theory.
[41] Gabor C. Temes,et al. Understanding Delta-Sigma Data Converters , 2004 .