Towards Fault-Tolerant RF Front Ends

The continuing trends of scaling have brought with them an ever-increasing array of process faults and fabrication complexities. The relentless march towards miniaturization and massive integration, in addition to increasing operating frequencies has resulted in increasing concerns about the reliability of integrated RF front-ends. Coupled with rising cost per chip, the fault-tolerant paradigm has become pertinent in the RFIC domain. Due to the high frequencies involved, traditional fault-tolerance methods used in digital and lower frequency analog circuits cannot be applied. We propose a unique methodology to achieve fault-tolerance in RF circuits through dynamic sensing and on-chip self-correction, along with the development of robust algorithms. This technique, which poses minimal overheads and is transparent during ‘normal’ use of the circuit, is demonstrated on a cascode LNA, since the LNA is critical for the performance of the entire front-end. We present simulation and fabricated results of the system designed in IBM 0.25 μm CMOS 6RF process.

[1]  Martin Margala,et al.  A current sensor for on-chip, non-intrusive testing of RF systems , 2004, 17th International Conference on VLSI Design. Proceedings..

[2]  Chan-Hong Park,et al.  A low power CMOS Bluetooth transceiver with a digital offset canceling DLL-based GFSK demodulator , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[3]  Michael S. Heutmaker,et al.  An architecture for self-test of a wireless communication system using sampled IQ modulation and boundary scan , 1999, IEEE Commun. Mag..

[4]  J.C. Leete,et al.  A 2.4 GHz CMOS transceiver for Bluetooth , 2001, 2001 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium (IEEE Cat. No.01CH37173).

[5]  D.J. Allstot,et al.  Parasitic-aware design and optimization of CMOS RF integrated circuits , 1998, 1998 IEEE MTT-S International Microwave Symposium Digest (Cat. No.98CH36192).

[6]  Ali M. Niknejad,et al.  Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs , 1998, IEEE J. Solid State Circuits.

[7]  Mustapha Slamani,et al.  A low-cost test solution for wireless phone RFICs , 2003, IEEE Commun. Mag..

[8]  J.M.V. dos Santos,et al.  Fault-tolerance: new trends for digital circuits , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

[9]  M. Jarwala,et al.  End-to-end test strategy for wireless systems , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[10]  Chuan Yi Tang,et al.  A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..

[11]  Tejasvi Das,et al.  Use of source degeneration for non-intrusive BIST of RF front-end circuits , 2005, 2005 IEEE International Symposium on Circuits and Systems.