Automatic instruction code generation based on trellis diagrams

Automatic generation of efficient instruction code for integrated digital signal processors is addressed. Since these processors are primarily used in real-time applications, the instruction code has to meet high quality requirements. For this reason, the author is interested in generating optimal or at least highly optimized code regarding its execution time. However, in general, conventional compiler design techniques do not lead to satisfactory results because signal processors and microprocessors are very different in architecture. The algorithm for automatic instruction code generation presented here is based on a target machine description by trellis diagrams. It can be applied to generating efficient instruction code for a large number of modern integrated digital signal processors.<<ETX>>

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