Reinforce Memory Error Protection by Breaking DRAM Disturbance Correlation Within ECC Words

Row-hammering attack is increasingly a concern to computer security and reliability, particularly for computer servers using chipkill correct memories, which are vulnerable to row-hammering attack because of disturbance correlation within ECC words. Probabilistic Adjacent Row Activation (PARA) can effectively lower the probability of successful row-hammering attack, but its strength can be significantly weakened by simultaneous attacks on many rows. This paper presents a novel hardware design to reinforce the chipkill correct memory by breaking the disturbance correlation within individual ECC words. It uses an XOR-based, device-specific row remapping such that a single PARA breach can only disturb any ECC word on at most one memory device. A row-hammering attack has to breach the PARA defense twice to cause uncorrectable or undetectable errors, which is much more challenging than before. A case of evaluation shows that the solution increases the memory MTTF from 0.144 to over 300,000 years. The design incurs negligible performance and energy overheads.

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