Ultra-Low Power Static Logic Circuits Design in Subthreshold Region
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[1] Anantha Chandrakasan,et al. Sub-threshold Design for Ultra Low-Power Systems , 2006, Series on Integrated Circuits and Systems.
[2] James D. Meindl,et al. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration , 2002, IEEE J. Solid State Circuits.
[3] A.P. Chandrakasan,et al. A 65 nm Sub-$V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter , 2008, IEEE Journal of Solid-State Circuits.
[4] David Blaauw,et al. Analysis and mitigation of variability in subthreshold design , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..
[5] Yusuf Leblebici,et al. Extreme Low-Power Mixed Signal IC Design , 2010 .
[6] Saibal Mukhopadhyay,et al. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.
[7] Armin Tajalli,et al. Extreme Low-Power Mixed Signal IC Design: Subthreshold Source-Coupled Circuits , 2010 .