论文信息 - An Approach for Four Way Set Associative Multilevel CMOS Cache Memory

An Approach for Four Way Set Associative Multilevel CMOS Cache Memory

The approach for design of four way set associative multilevel CMOS cache memory is discussed here. The cache hierarchy, organization and cache structure has been discussed. Apart from these the two levels i.e. level 1 & level 2 of cache memory design approach are discussed. The type of cache memory organization to be used is the major part design. The approach for the design of CMOS cache memory uses set associative mapping over the other cache organization as set associative mapping uses several direct-mapped caches which is referred as set. This four way set associative cache memory can be used for VLSI systems in computer and wireless communication systems.

A. Y. Deshmukh | Prasanna Palsodkar | Preeti R. Bajaj | Avinash Keskar

[1] A. K. Goksel,et al. A content addressable memory management unit with on-chip data cache , 1989 .

[2] J. Miyake,et al. An 8-kbit content-addressable and reentrant memory , 1985, IEEE Journal of Solid-State Circuits.

[3] James B. Kuo,et al. A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme , 2002 .

[4] James B. Kuo,et al. Low-voltage CMOS VLSI circuits , 1999 .

[5] Norman P. Jouppi,et al. Tradeoffs in two-level on-chip caching , 1994, ISCA '94.

[6] Koichiro Ishibashi,et al. A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators , 1996 .

[7] James B. Kuo,et al. A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell , 2001 .