Radiation-Hardened Structure to Reduce Sensitive Range of a Stacked Structure for FDSOI

Flip-flops (FFs) with stacked transistors have high radiation tolerance in a fully depleted silicon on insulator (FDSOI) process. However, the FFs are weak against a radioactive particle hit with high linear energy transfer (LET) and from high incident angles. In this paper, we used heavy-ion irradiation tests to evaluate the soft-error tolerance of a stacked structure and a radiation-hardened structure in an attempt to reduce sensitive range (RSR). We propose a novel FF with the RSR structure. We fabricate a chip in a 65-nm FDSOI process with three latches, each with different distances between stacked transistors. Experimental results reveal that the stacked structures are weak against a heavy-ion hit that exceeds a LET of 60 MeV<inline-formula> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula>cm<sup>2</sup>/mg even though the distance between stacked transistors was increased from 250 to 350 nm. We evaluated the RSR structure by TCAD simulations and measured the radiation hardness of the proposed FF by heavy-ion irradiation on the fabricated chips. Measurement by heavy ions with LET of 67.2 MeV<inline-formula> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula>cm<sup>2</sup>/mg at all angles show no detectable errors in the proposed FF.

[1]  J. Furuta,et al.  A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI , 2014, IEEE Transactions on Nuclear Science.

[2]  Philippe Roche,et al.  Technology downscaling worsening radiation effects in bulk: SOI to the rescue , 2013, 2013 IEEE International Electron Devices Meeting.

[3]  N. Sugii,et al.  Local $V_{\rm th}$ Variability and Scalability in Silicon-on-Thin-BOX (SOTB) CMOS With Small Random-Dopant Fluctuation , 2010, IEEE Transactions on Electron Devices.

[4]  S. Matsuda,et al.  Hardness-by-design approach for 0.15 /spl mu/m fully depleted CMOS/SOI digital logic devices with enhanced SEU/SET immunity , 2005, IEEE Transactions on Nuclear Science.

[5]  Kazutoshi Kobayashi,et al.  Radiation hardness evaluations of 65 nm fully depleted silicon on insulator and bulk processes by measuring single event transient pulse widths and single event upset rates , 2015 .

[6]  Kazutoshi Kobayashi,et al.  A non-redundant low-power flip flop with stacked transistors in a 65 nm thin BOX FDSOI process , 2016, 2016 16th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

[7]  J. Barth,et al.  Model for Cumulative Solar Heavy Ion Energy and Linear Energy Transfer Spectra , 2007, IEEE Transactions on Nuclear Science.

[8]  Nobuyuki Sano,et al.  Multi-scale Monte Carlo simulation of soft errors using PHITS-HyENEXSS code system , 2011, 2011 12th European Conference on Radiation and Its Effects on Components and Systems.

[9]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[10]  Kazutoshi Kobayashi,et al.  A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process , 2018, IEICE Trans. Electron..

[11]  Kazutoshi Kobayashi,et al.  Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process , 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

[12]  H. Asai,et al.  SEE in a 0.15 /spl mu/m fully depleted CMOS/SOI commercial Process , 2004, IEEE Transactions on Nuclear Science.

[13]  T. D. Loveless,et al.  Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node , 2011, IEEE Transactions on Nuclear Science.

[14]  Kazutoshi Kobayashi,et al.  Radiation-Hardened Flip-Flops With Low-Delay Overhead Using pMOS Pass-Transistors to Suppress SET Pulses in a 65-nm FDSOI Process , 2018, IEEE Transactions on Nuclear Science.

[15]  P. Eaton,et al.  Soft error rate mitigation techniques for modern microcircuits , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[16]  J. S. Kauppila,et al.  Utilizing device stacking for area efficient hardened SOI flip-flop designs , 2014, 2014 IEEE International Reliability Physics Symposium.

[17]  Vivek De,et al.  Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process , 2004 .

[18]  K. Soumyanath,et al.  Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..