Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies

This paper presents a feasible study of fully-integrated switching voltage regulators for power-optimized systems-on-chip (SoCs). In order to evaluate the power efficiency across a number of design variables, a compact macro-model of a regulator is created and validated. A key focus of the study is on the characteristics of the active and passive devices that are needed in order to maximize the efficiency of an on-chip regulator. With the macro-model, geometric programming is used to find the optimal characteristics for a given set of constraints such as load condition, process technology, and area. The achievable efficiencies for various current loads and across a range of technologies from 0.35-mum to 90-nm CMOS process are analyzed. The power efficiency is found to be strongly dependent on the inductor technology and over 70% efficiency is possible with advanced inductor technologies.

[1]  A. Maxim.  Notice of Violation of IEEE Publication PrinciplesA 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation , 2005, IEEE Journal of Solid-State Circuits.

[2]  F. C. Lee,et al.  A family of novel interleaved DC/DC converters for low-voltage high-current voltage regulator module applications , 2001, 2001 IEEE 32nd Annual Power Electronics Specialists Conference (IEEE Cat. No.01CH37230).

[3]  Shan X. Wang,et al.  High-frequency microinductors with amorphous magnetic ground planes , 2002 .

[4]  Teresa H. Meng,et al.  A high-efficiency variable-voltage CMOS dynamic dc-dc switching regulator , 1997 .

[5]  Stephen P. Boyd,et al.  Optimal design of a CMOS op-amp via geometric programming , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  B. Razavi.  The Modeling, Characterization, and Design of Monolithic Inductors for Silicon RF IC's , 2003 .

[7]  Stephen P. Boyd,et al.  Simple accurate expressions for planar spiral inductances , 1999, IEEE J. Solid State Circuits.

[8]  Ali M. Niknejad,et al.  Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs , 1998, IEEE J. Solid State Circuits.

[9]  C. Lichtenau,et al.  A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features , 2005, IEEE Journal of Solid-State Circuits.

[10]  Stefan Rusu,et al.  A 400-MT/s 6.4-GB/s multiprocessor bus interface , 2003 .

[11]  Shan X. Wang,et al.  High frequency (GHz) and low resistance integrated inductors using magnetic materials , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[12]  Chih-Kong Ken Yang,et al.  Techniques for improving the accuracy of geometric-programming based analog circuit design optimization , 2004, ICCAD 2004.

[13]  J.D. Meindl,et al.  Complementary adiabatic and fully adiabatic MOS logic families for gigascale integration , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[14]  C. Patrick Yue,et al.  Design strategy of on-chip inductors for highly integrated RF systems , 1999, DAC '99.