Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits

The challenges to design engineers have been complicated due to the introduction of nanoscale process variation into the design phase. One of the ways to analyze the circuit behaviors under process variation is to determine the rare events that may be originated due to such process variation. A method called Statistical Blockade (SB) had been investigated to estimate the rare events statistics especially for high-replication circuits [1]. An enhanced statistical blockade method is proposed in this paper which is shown to be much faster compared to the traditional exhaustive Monte Carlo simulation. In SB, the classification threshold determination is quite important for different tail regions which is related to the number of rare events simulation. This paper presents the values of classification threshold tc for different tail regions of typical circuits and the training samples size n required for corresponding tc. It offers both fastest speed of simulation and highest accuracy for the proposed Statistical Blockade method. It is also proven that the obtained tc can be used for all the technology corners. The enhanced statistical blockade method thus performs fast estimate the robustness for different designs. In the proposed method, the tail part of the whole distribution is used in estimation; thereby saving time. It shows 7.3× faster than traditional evaluation methods. Furthermore, for the design which is proved to be robust even in worst-case, the optimal body bias voltage is applied to improve the performance and power while reducing the variability with Adaptive Body Bias (ABB) technique. Index Terms Statistical Blockade Method, Robustness Circuits, Nanoscale CMOS, Arithmetic Circuits, Monte Carlo, Rare Event