Comparison frequency doubling and charge pump matching techniques for dual-band /spl Delta//spl Sigma/ fractional-N frequency synthesizer

The frequency synthesizer with two LC-VCOs is fully integrated in a 0.35-/spl mu/m CMOS technology. In supporting dual bands, all building blocks except VCOs are shared. A current compensation scheme using a replica charge pump improves the linearity of the frequency synthesizer and, thus, suppresses spurious tones. To reduce the quantization noise from a /spl Delta//spl Sigma/ modulator and the noise from the building blocks except the VCO, the proposed architecture uses a frequency doubler with a noise-insensitive duty-cycle correction circuit (DCC) in the reference clock path. Power consumption is 37.8 mW with a 2.7-V supply. The proposed frequency synthesizer supports 10-kHz channel spacing with the measured phase noise of -114 dBc/Hz and -141 dBc/Hz at 100-kHz and 1.25-MHz offsets, respectively, in the PCS band. The fractional spurious tone at 10-kHz offset is under -54 dBc.

[1]  W. Rhee,et al.  An on-chip phase compensation technique in fractional-N frequency synthesis , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[2]  R. Schreier,et al.  Delta-sigma data converters : theory, design, and simulation , 1997 .

[3]  Scott E. Meninger,et al.  A fractional- N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise , 2003 .

[4]  B. Miller,et al.  A multiple modulator fractional divider , 1990, 44th Annual Symposium on Frequency Control.

[5]  Deog-Kyoon Jeong,et al.  A fully-integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[6]  Behzad Razavi.  A Modeling Approach for ¿¿ FractionalN Frequency Synthesizers Allowing Straightforward Noise Analysis , 2003 .

[7]  B.-S. Song,et al.  A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order /spl Delta//spl Sigma/ modulator , 2000, IEEE Journal of Solid-State Circuits.

[8]  M. Steyaert,et al.  A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800 , 2002, IEEE J. Solid State Circuits.

[9]  Juha Kostamovaara,et al.  Techniques for in-band phase noise reduction in /spl Delta//spl Sigma/ synthesizers , 2003 .

[10]  Michael H. Perrott,et al.  A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation , 1997, IEEE J. Solid State Circuits.

[11]  Kang-Yoon Lee,et al.  A CMOS dual-band fractional-n synthesizer with reference doubler and compensated charge pump , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[12]  T. Riley,et al.  Delta-sigma modulation in fractional-N frequency synthesis , 1993 .

[13]  Asad A. Abidi,et al.  RF-CMOS oscillators with switched tuning , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[14]  M. A. Copeland,et al.  for Fractional- Frequency Synthesis , 1999 .

[15]  Mitchell D. Trott,et al.  A Modeling Approach for – Fractional- N Frequency Synthesizers Allowing Straightforward Noise Analysis , 2001 .

[16]  W. Rhee,et al.  Design of high-performance CMOS charge pumps in phase-locked loops , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[17]  Shin-Il Lim,et al.  Charge pump with perfect current matching characteristics in phase-locked loops , 2000 .

[18]  M. A. Copeland,et al.  Design and realization of a digital /spl Delta//spl Sigma/ modulator for fractional-n frequency synthesis , 1999 .

[19]  Bram De Muer,et al.  On the analysis of ΔΣ fractional-N frequency synthesizers for high-spectral purity , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[20]  Michiel Steyaert,et al.  Wireless CMOS Frequency Synthesizer Design , 1998 .