Evaluation of Hardware Performance for the SHA-3 Candidates Using SASEBO-GII
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[1] A. H. Namin,et al. Hardware Implementation of the Compression Function for Selected SHA-3 Candidates , 2009 .
[2] Ingrid Verbauwhede,et al. Iteration Bound Analysis and Throughput Optimum Architecture of SHA-256 (384, 512) for Hardware Implementations , 2007, WISA.
[3] Steffen Reith,et al. On Optimized FPGA Implementations of the SHA-3 Candidate Groestl , 2009, IACR Cryptol. ePrint Arch..
[4] Patrick Schaumont,et al. A Hardware Interface for Hashing Algorithms , 2008, IACR Cryptol. ePrint Arch..
[5] Martin Feldhofer,et al. High-Speed Hardware Implementations of BLAKE, Blue Midnight Wish, CubeHash, ECHO, Fugue, Gröstl, Hamsi, JH, Keccak, Luffa, Shabal, SHAvite-3, SIMD, and Skein , 2009, IACR Cryptol. ePrint Arch..
[6] William P. Marnane,et al. FPGA Implementations of SHA-3 Candidates: CubeHash, Grøstl, LANE, Shabal and Spectral Hash , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.