Design theory and implementation for low-power segmented bus systems

The concept of bus segmentation has been proposed to minimize power consumption by reducing the switched capacitance on each bus [Chen et al. 1999]. This paper details the design theory and implementation issues of segmented bus systems. Based on a graph model and the Gomory-Hu cut-equivalent tree algorithm, a bus can be partitioned into several bus segments separated by pass transistors. Highly communicating devices are placed to adjacent bus segments, so most data communication can be achieved by switching a small portion of the bus segments. Thus, a significant amount of power consumption can be saved. It can be proved that the proposed bus partitioning method achieves an optimal solution. The concept of tree clustering is also proposed to merge bus segments for further power reduction. The design flow, which includes bus tree construction in the register-transfer level and bus segmentation cell placement and routing in the physical level, is discussed for design implementation. The technology has been applied to a μ-controller design, and simulation results by PowerMill show significant improvement in power consumption.

[1]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[2]  Mircea R. Stan,et al.  Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Jan M. Rabaey,et al.  A partitioning scheme for optimizing interconnect power , 1997, IEEE J. Solid State Circuits.

[4]  A. Bellaouar,et al.  An ultra-low-power CMOS on-chip interconnect architecture , 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.

[5]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[6]  H. Samueli,et al.  A 300 MHz digital double-sideband to single-sideband converter in 1 /spl mu/m CMOS , 1995 .

[7]  Baher Haroun,et al.  A novel reduced swing CMOS bus interface circuit for high speed low power VLSI systems , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[8]  Joan Figueras,et al.  Power optimization of delay constrained CMOS bus drivers , 1996, Proceedings ED&TC European Design and Test Conference.

[9]  Mitsuru Hiraki,et al.  Data-Dependent Logic Swing Internal Bus Architecture for Ultra-Low-Power Lsis , 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

[10]  David Hartvigsen,et al.  Multiterminal flows and cuts , 1995, Oper. Res. Lett..

[11]  Yuval Tamir.  Self-checking self-repairing computer nodes using the Mirror Processor , 1992 .

[12]  S. Watanabe,et al.  BICMOS circuit technology for high speed DRAMs , 1987, 1987 Symposium on VLSI Circuits.

[13]  T. C. Hu,et al.  Multi-Terminal Network Flows , 1961 .

[14]  I. Scott MacKenzie,et al.  The 8051 Microcontroller , 1992 .

[15]  Mircea R. Stan,et al.  Coding a terminated bus for low power , 1995, Proceedings. Fifth Great Lakes Symposium on VLSI.

[16]  Kiyoo Itoh,et al.  Sub 1V Swing Internal Bus Architecture for Future Low-Power ULSI's (Special Section on the 1992 VLSI Circuits Symposium) , 1993 .

[17]  Dake Liu,et al.  Power consumption estimation in CMOS VLSI chips , 1994, IEEE J. Solid State Circuits.

[18]  Kiyoo Itoh,et al.  Sub-1-V swing internal bus architecture for future low-power ULSIs , 1993 .

[19]  Gian Carlo Cardarilli,et al.  Bus architecture for low-power VLSI digital circuits , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[20]  Makoto Ikeda,et al.  A reduced-swing data transmission scheme for resistive bus lines in VLSIs , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[21]  T. F. Chen,et al.  Segmented bus design for low-power systems , 1999, IEEE Trans. Very Large Scale Integr. Syst..