Frequency Analysis Method for Propagation of Transient Errors in Combinational Logic
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[1] Bharat L. Bhuva,et al. Simulation of SEU transients in CMOS ICs , 1991 .
[2] Sung-Mo Kang,et al. Fast timing simulation of transient faults in digital circuits , 1994, ICCAD.
[3] Kartik Mohanram,et al. Simulation of transients caused by single-event upsets in combinational logic , 2005, IEEE International Conference on Test, 2005..
[4] Peter Lidén,et al. A switch-level algorithm for simulation of transients in combinational logic , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[5] Mark Horowitz,et al. Timing Models for MOS Circuits , 1983 .
[6] Ming Zhang,et al. A soft error rate analysis (SERA) methodology , 2004, ICCAD 2004.
[7] Nihar R. Mahapatra,et al. Combining error masking and error detection plus recovery to combat soft errors in static CMOS circuits , 2005, 2005 International Conference on Dependable Systems and Networks (DSN'05).
[8] Hyungsoon Shin. Modeling of alpha-particle-induced soft error rate in DRAM , 1999 .
[9] C. Metra,et al. A model for transient fault propagation in combinatorial logic , 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..
[10] Lorenzo Alvisi,et al. Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.
[11] Janak H. Patel,et al. A logic-level model for /spl alpha/-particle hits in CMOS circuits , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.
[12] Elizabeth M. Rudnick,et al. A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults , 1996, IEEE Trans. Computers.
[13] Gwan S. Choi,et al. A design approach for radiation-hard digital electronics , 2006, 2006 43rd ACM/IEEE Design Automation Conference.