论文信息 - A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications

A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications

This document summarizes, for the university design contest, a chip design of a low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) in a 0.18 μm CMOS process. Power dissipation of this chip is 350 μW including the output buffers. The die area is 0.081mm2.

Daisuke Kanemoto | Keigo Oshiro | Keiji Yoshida | Haruichi Kanaya

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