Soft Error Analysis and Optimizations of C-elements in Asynchronous Circuits

Control circuit in an asynchronous design is comprised mostly of Muller C-elements. Previous work has concentrated on power, performance, and area issues of various CMOS implementations of the C-element. In this paper we carried out a thorough soft error analysis of four popular CMOS implementations of the Muller C-element. It shows that SIL implementation has the best soft error resilience. Optimization techniques to improve the soft error resilience of C-elements are proposed. Results show 2x improvements in critical charge by using our techniques. Finally, analysis of power, performance, and area tradeoff is carried out for the optimized C-element.

[1]  Bella Bose,et al.  Balanced codes for noise reduction in VLSI systems , 1994, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing.

[2]  Mohamed I. Elmasry,et al.  Optimizing CMOS implementations of the C-element , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[3]  Mohamed I. Elmasry,et al.  A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element , 1996, ISLPED.

[4]  Scott Hauck,et al.  Asynchronous design methodologies: an overview , 1995, Proc. IEEE.

[5]  Steven M. Nowick,et al.  Scanning the Technology Applications of Asynchronous Circuits , 1999 .

[6]  Nitin H. Vaidya,et al.  Limitations of VLSI implementation of delay-insensitive codes , 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.

[7]  Jehoshua Bruck,et al.  Unordered error-correcting codes and their applications , 1992, [1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing.

[8]  Rajit Manohar,et al.  Fault detection and isolation techniques for quasi delay-insensitive circuits , 2004, International Conference on Dependable Systems and Networks, 2004.

[9]  Kees van Berkel Beware the isochronic fork , 1992, Integr..

[10]  Alain J. Martin,et al.  Quasi-Delay-Insensitive Circuits are Turing-Complete , 1995 .

[11]  Fu-Chiung Cheng,et al.  Efficient systematic error-correcting codes for semi-delay-insensitive data transmission , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

[12]  N. Seifert,et al.  Robust system design with built-in soft-error resilience , 2005, Computer.

[13]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[14]  Ivan E. Sutherland,et al.  Micropipelines , 1989, Commun. ACM.

[15]  R. Baumann Soft errors in advanced semiconductor devices-part I: the three radiation sources , 2001 .

[16]  Kartik Mohanram,et al.  Cost-effective radiation hardening technique for combinational logic , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[17]  S. Vangal,et al.  Selective node engineering for chip-level soft error rate improvement [in CMOS] , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[18]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[19]  N. R. Poole Self-timed logic circuits , 1994 .

[20]  A. J. Martin Formal program transformations for VLSI circuit synthesis , 1989 .

[21]  Régis Leveugle,et al.  Asynchronous circuits transient faults sensitivity evaluation , 2005, Proceedings. 42nd Design Automation Conference, 2005..