Novel Electrical and Fluidic Microbumps for Silicon Interposer and 3-D ICs

Fine-pitch electrical microbumps (25-μm diameter and 50-μm pitch) and annular-shaped fluidic microbumps (150-μm inner diameter and 210-μm outer diameter) are presented to enable high-bandwidth die-to-die signaling, embedded microfluidic cooling and power delivery for silicon interposer and 3-D integrated electronic systems. Electrical and fluidic testing demonstrates good bonding of the electrical and fluidic microbumps; the average resistance of a single electrical microbump is 13.5 mQ. The bonded fluidic microbumps are successfully tested up to 100 kPa without any leakage. Moreover, the power supply noise (PSN) of 3-D chip stacks is analyzed using a compact physical model. Based on the model, increasing the number of power/ground pads is effective in suppressing PSN, motivating the need for fine-pitch electrical microbumps. Impact of the number of dice in a stack, die thickness, and the area of on-die decoupling capacitors on PSN is also investigated.

[1]  R. Pease,et al.  High-performance heat sinking for VLSI , 1981, IEEE Electron Device Letters.

[2]  M. Massoud Engineering Thermofluids: Thermodynamics, Fluid Mechanics, and Heat Transfer , 2005 .

[3]  Keith A. Jenkins,et al.  Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection , 2005, IBM J. Res. Dev..

[4]  K. Shakeri,et al.  Compact physical IR-drop models for chip/package co-design of gigascale integration (GSI) , 2005, IEEE Transactions on Electron Devices.

[5]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[6]  P. Andry,et al.  Characterization of micro-bump C4 interconnects for Si-carrier SOP applications , 2006, 56th Electronic Components and Technology Conference 2006.

[7]  Gang Huang,et al.  Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication , 2007, 2007 IEEE Electrical Performance of Electronic Packaging.

[8]  Madhavan Swaminathan,et al.  Power Integrity Modeling and Design for Semiconductors and Systems , 2007 .

[9]  T. Kurihara,et al.  Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring , 2008, 2008 58th Electronic Components and Technology Conference.

[10]  Muhannad S. Bakir,et al.  Integrated Interconnect Technologies for 3D Nanoelectronic Systems , 2008 .

[11]  Philip G. Emma,et al.  Is 3D chip technology the next growth engine for performance improvement? , 2008, IBM J. Res. Dev..

[12]  Muhannad S. Bakir,et al.  3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[13]  J. Meindl,et al.  Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips , 2010, IEEE Transactions on Advanced Packaging.

[14]  B. Dang,et al.  3D Chip stacking with 50 μm pitch lead-free micro-c4 interconnections , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[15]  S. Rylov,et al.  An 8×10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[16]  M. Bakir,et al.  Coupled electrical and thermal 3D IC centric microfluidic heat sink design and technology , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[17]  Dongwook Kim,et al.  Interposer design optimization for high frequency signal transmission in passive and active interposer using through silicon via (TSV) , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[18]  B. Banijamali,et al.  Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA , 2011, Electronic Components and Technology Conference.

[19]  Soha Hassoun,et al.  Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Raghunandan Chaware,et al.  Assembly process integration challenges and reliability assessment of multiple 28nm FPGAs assembled on a Large 65nm passive interposer , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[21]  Gang Huang,et al.  Power Delivery for 3-D Chip Stacks: Physical Modeling and Design Implication , 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[22]  M. Brillhart,et al.  Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[23]  Yong Liu,et al.  An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects , 2012, IEEE Journal of Solid-State Circuits.

[24]  M. Bakir,et al.  3D stacked microfluidic cooling for high-performance 3D ICs , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[25]  Muhannad S. Bakir,et al.  Silicon Micropin-Fin Heat Sink With Integrated TSVs for 3-D ICs: Tradeoff Analysis and Experimental Testing , 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.