Trends in compilable DSP architecture

We review the evolution of DSP architectures and compiler technology, and describe how compiler techniques are being used to optimize emerging DSP architectures. Such new architectures are characterized by the exploitation of data and instruction level parallelism while being an amenable target for a compiler, thereby reducing or eliminating the need to rely on assembly language programming and/or architecture-specific compiler intrinsics to achieve highly efficient code. We also summarize our research results on an ultra low power compilable DSP architecture.

[1]  Jennifer Eyre,et al.  DSP Processors Hit the Mainstream , 1998, Computer.

[2]  Bryan D. Ackland,et al.  A single-chip 1.6 billion 16-b MAC/s multiprocessor DSP , 1999 .

[3]  M. Gagnaire,et al.  An overview of broad-band access technologies , 1997, Proc. IEEE.

[4]  N. Pitsianis.  A Kronecker Compiler for Fast Transform Algorithms ∗ , 1997 .

[5]  Gottfried Ungerboeck,et al.  Architecture of a Digital Signal Processor , 1985, IBM J. Res. Dev..

[6]  R. Tolimieri,et al.  The tensor product: a mathematical programming language for FFTs and other fast DSP operations , 1992, IEEE Signal Processing Magazine.

[7]  Erik R. Altman,et al.  Compiler/architecture interaction in a tree-based VLIW processor , 1997 .

[8]  Richard M. Stallman,et al.  Using and Porting GNU CC , 1998 .

[9]  K. W. Leary,et al.  DSP/C: a standard high level language for DSP and numeric processing , 1990, International Conference on Acoustics, Speech, and Signal Processing.

[10]  Uri C. Weiser,et al.  MMX technology extension to the Intel architecture , 1996, IEEE Micro.

[11]  Jan M. Rabaey,et al.  Predicting performance potential of modern DSPs , 2000, Proceedings 37th Design Automation Conference.

[12]  Lizy Kurian John,et al.  Exploiting SIMD parallelism in DSP and multimedia algorithms using the AltiVec technology , 1999, ICS '99.

[13]  B. Ackland,et al.  A new generation of DSP architectures , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[14]  Edward A. Lee,et al.  DSP Processor Fundamentals , 1997 .

[15]  Thomas M. Conte,et al.  Compiler-driven cached code compression schemes for embedded ILP processors , 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.

[16]  Z. Greenfield,et al.  The TigerSHARC DSP Architecture , 2000, IEEE Micro.

[17]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.

[18]  C. John Glossner,et al.  A new approach to DSP intrinsic functions , 2000, Proceedings of the 33rd Annual Hawaii International Conference on System Sciences.

[19]  E. Sackinger,et al.  A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP , 2000, IEEE Journal of Solid-State Circuits.