Copper pillar bump structure optimization for flip chip packaging with Cu/Low-K stack
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A. Yeo | W.H. Zhu | W.H. Zhu | X.R. Zhang | A. Yeo | X.R. Zhang | B.P. Liew | M. Gaurav | K.C. Chan | K.C. Chan | B. P. Liew | M. Gaurav
[1] K. M. Chen,et al. Copper pillar bump design optimization for lead free flip-chip packaging , 2010 .
[2] Development of Novel Joint Resistance Modeling Technique for Flip Chip Interconnection Systems , 2006, 2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium.
[3] T. Jiang,et al. Intermetallic Formation of Copper Pillar With Sn–Ag–Cu for Flip-Chip-On-Module Packaging , 2008, IEEE Transactions on Components and Packaging Technologies.
[4] Reliability Study on Copper Pillar Bumping with Lead Free Solder , 2007, 2007 9th Electronics Packaging Technology Conference.