An embedded processor core for consumer appliances with 2.8GFLOPS and 36M polygons/s FPU

An embedded-processor core implemented in a 130nm CMOS process runs at 400MHz and achieves 720MIPS with a power of 250mW and 2.8GFLOPS. The processor employs a dual-issue seven-stage pipeline architecture while maintaining 1.8MIPS/MHz instruction efficiency of the previous five-stage processor. The processor is suitable for digital consumer appliances.

[1]  Y. Yasu,et al.  A resume-standby application processor for 3G cellular phones , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[2]  Kevin J. Nowka,et al.  Leading zero anticipation and detection-a comparison of methods , 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

[3]  R. Rogenmoser,et al.  A dual-issue floating-point coprocessor with SIMD architecture and fast 3D functions , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[4]  R. Satomura,et al.  A 133 MHz 170 mW 10 /spl mu/A standby application processor for 3G cellular phones , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).