Design Optimization of Metal Nanocrystal Memory—Part I: Nanocrystal Array Engineering

The three-dimensional (3D) electrostatics together with the modified Wentzel-Kramers-Brillouin tunneling model has been implemented to simulate the programming and retention characteristics of the metal nanocrystal (NC) memories. Good agreements with experimental data are first demonstrated to calibrate the transport parameters. In contrast to previous works, the 3D electrostatic effects investigated in this paper are proven very significant in the memory operations. Therefore, new design criteria of metal NC memories are investigated. Part I presents the physical model and the NC array design optimization. A sparse and large-size NC array, which is suitable for the one-dimensional narrow-channel memories, provides higher program/erase tunneling current density due to the field-enhancement effect and lower charging energy due to the large NC capacitance. On the other hand, to achieve a sufficient memory window, fast programming speed, and long retention time in the typical two-dimensional channel memories, a dense and large-size NC array is favorable while taking the tradeoff with the NC number density into account. Based on the same theoretical model, the authors continue in Part II to consider the design optimization when high-K dielectrics can be employed

[1]  Chuanbin Mao,et al.  Protein-Mediated Nanocrystal Assembly for Flash Memory Fabrication , 2007, IEEE Transactions on Electron Devices.

[2]  Tuo-Hung Hou,et al.  Design Optimization of Metal Nanocrystal Memory—Part II: Gate-Stack Engineering , 2006, IEEE Transactions on Electron Devices.

[3]  U. Ganguly,et al.  Asymmetric electric field enhancement in nanocrystal memories , 2005, IEEE Electron Device Letters.

[4]  S.K. Banerjee,et al.  Nanocrystal flash memory fabricated with protein-mediated assembly , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[5]  E. Kan,et al.  Carbon nanotube-based nonvolatile memory with charge storage in metal nanocrystals , 2005 .

[6]  D. Ielmini,et al.  Modeling of tunneling P/E for nanocrystal memories , 2005, IEEE Transactions on Electron Devices.

[7]  Dim-Lee Kwong,et al.  Metal nanocrystal memory with high-/spl kappa/ tunneling barrier for improved data retention , 2005 .

[8]  Edwin C. Kan,et al.  Self-assembly of metal nanocrystals on ultrathin oxide for nonvolatile memory applications , 2005 .

[9]  G. Atwood,et al.  Future directions and challenges for ETox flash memory scaling , 2004, IEEE Transactions on Device and Materials Reliability.

[10]  E. Kan,et al.  Characterization of Number Fluctuations in Gate-last Metal Nanocrystal Nonvolatile Memory Array beyond 90nm CMOS Technology , 2004 .

[11]  M. Koyanagi,et al.  New non-volatile memory with extremely high density metal nano-dots , 2003, IEEE International Electron Devices Meeting 2003.

[12]  E. Kan,et al.  Operational and reliability comparison of discrete-storage nonvolatile memories: advantages of single- and double-layer metal nanocrystals , 2003, IEEE International Electron Devices Meeting 2003.

[13]  Y. Zhang,et al.  Low voltage, scalable nanocrystal flash memory fabricated by templated self assembly , 2003, IEEE International Electron Devices Meeting 2003.

[14]  Gerard Ghibaudo,et al.  Modeling of the programming window distribution in multinanocrystals memories , 2003 .

[15]  Tsu-Jae King,et al.  Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance , 2003 .

[16]  T. Hiramoto,et al.  Large memory window and long charge-retention time in ultranarrow-channel silicon floating-dot memory , 2003 .

[17]  G. Pei,et al.  Metal nanocrystal memories. I. Device design and fabrication , 2002 .

[18]  G. Pei,et al.  Metal nanocrystal memories-part II: electrical characteristics , 2002 .

[19]  Y. Hou,et al.  Direct tunneling hole currents through ultrathin gate oxides in metal-oxide-semiconductor devices , 2002 .

[20]  Gerard Ghibaudo,et al.  Experimental and theoretical investigation of nano-crystal and nitride-trap memory devices , 2001 .

[21]  Enrico Sangiorgi,et al.  Tunneling into interface states as reliability monitor for ultrathin oxides , 2000 .

[22]  Extraction of the gate oxide thickness of N- and P-Channel MOSFETs below 20 /spl Aring/ from the substrate current resulting from valence-band electron tunneling , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[23]  J. Wortman,et al.  Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices , 1999 .

[24]  Sandip Tiwari,et al.  Kinetic modelling of electron tunneling processes in quantum dots coupled to field-effect transistors , 1998 .

[25]  Lukas Novotny,et al.  Theory of Nanometric Optical Tweezers , 1997 .

[26]  Sandip Tiwari,et al.  Volatile and non-volatile memories in silicon with nano-crystal storage , 1995, Proceedings of International Electron Devices Meeting.

[27]  Joseph M. Crowley,et al.  Fundamentals of applied electrostatics , 1986 .