Power Aware Models : Overcoming barriers in Power Aware Simulation

The increasing presence of power management at earlier stages in the design cycle and its effect on functionality demands simulations at RTL stage to be power aware to ensure correctness of the power management. The presence of variety of pre-implemented complex IPs (hard macros) in a SoC often lack appropriate power aware simulation models, forcing users to rely on gate level or analog simulations for complete power aware verification. This limits the effectiveness of power aware simulations at RTL. Moreover, the presence of power management may introduce new IPs that act as power sources, supplying power to the supply network, additionally requiring power aware simulation models. In this paper, we will demonstrate how to extend existing models with power aware behavior and also their integration in the UPF environment for more accurate power aware simulations at RTL. Keywords—Power Aware Simulation; Hard Macros; Analog Macros; UPF; Liberty; Voltage Regulators; Power Sources