A Novel Capacitorless DRAM Cell Design Using Band-Gap Engineered Junctionless Double-Gate FET

This paper presents novel capacitor less dynamic random access memory (DRAM) cells through band-gap engineered silicon-germanium (SiGe) junction less double gate field effect transistor (JL-DGFET) using two-dimensional commercial TCAD device simulator. The design window of capacitor less DRAM cell and its operations have been described. We observe hysteresis current-voltage characteristic and steep change in sub-threshold slope (SS) in SiGe JL-DGFET. The correlation between the IDS - VGS and IDS - VDS characteristics of the device during different operation of memory cells are discussed. Furthermore, high value of bipolar gain (i.e. β) is observed in optimally designed SiGe JL-DGFET transistors, which can be utilized for the improvement of sensing margin in dynamic memories. The results presented in this paper can provide an opportunity for future DRAM design in deep nanometer technology.

[1]  M. J. Kumar,et al.  A Silicon Biristor With Reduced Operating Voltage: Proposal and Analysis , 2015, IEEE Journal of the Electron Devices Society.

[2]  S. Okhonin,et al.  New Generation of Z-RAM , 2007, 2007 IEEE International Electron Devices Meeting.

[3]  Yuan Taur,et al.  Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.

[4]  Akihiro Nitayama,et al.  Operation voltage dependence of memory cell characteristics in fully depleted floating-body cell , 2005, IEEE Transactions on Electron Devices.

[5]  Chenming Hu,et al.  A capacitorless double-gate DRAM cell , 2002, IEEE Electron Device Letters.

[6]  C. Mazure,et al.  Ultra-scaled Z-RAM cell , 2008, 2008 IEEE International SOI Conference.

[7]  P. Kapur,et al.  A Nanoscale Vertical Double-Gate Single-Transistor Capacitorless DRAM , 2008, IEEE Electron Device Letters.

[8]  Kiyoo Itoh,et al.  Limitations and challenges of multigigabit DRAM chip design , 1997, IEEE J. Solid State Circuits.

[9]  Jean-Pierre Colinge,et al.  Performance estimation of junctionless multigate transistors , 2010 .

[10]  Kinam Kim,et al.  DRAM technology perspective for gigabit era , 1998 .

[11]  S. Balakumar,et al.  Germanium-Rich SiGe Nanowires Formed Through Oxidation of Patterned SiGe FINs on Insulator , 2009 .

[12]  Yang‐Kyu Choi,et al.  A Bandgap-Engineered Silicon-Germanium Biristor for Low-Voltage Operation , 2014, IEEE Transactions on Electron Devices.

[13]  G. A. Armstrong,et al.  Bipolar effects in unipolar junctionless transistors , 2012 .

[14]  Chi-Woo Lee,et al.  Low subthreshold slope in junctionless multigate transistors , 2010 .

[15]  S. Balakumar,et al.  Ge-Rich (70%) SiGe Nanowire MOSFET Fabricated Using Pattern-Dependent Ge-Condensation Technique , 2008, IEEE Electron Device Letters.

[16]  Guo-Qiang Lo,et al.  I-MOS Transistor With an Elevated Silicon–Germanium Impact-Ionization Region for Bandgap Engineering , 2006, IEEE Electron Device Letters.

[17]  T. Skotnicki,et al.  A capacitor-less DRAM cell on 75nm gate length, 16nm thin fully depleted SOI device for high density embedded memories , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[18]  Jin-Woo Han,et al.  Bistable resistor (biristor) - gateless silicon nanowire memory , 2010, 2010 Symposium on VLSI Technology.

[19]  T. Tanaka,et al.  A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory , 2006, IEEE Transactions on Electron Devices.