Optimisation in behavioural synthesis using hierarchical expansion: module ripping

During behavioural synthesis, an abstract functional description of a system is mapped automatically onto a physical structure. In a competitive setting, this mapping will be highly optimised - the dataflow is re-arranged, units and registers are multiplexed and so on - to deliver a final structure that meets some overall user supplied specification. Ultimately, however, the physical functional units are drawn from some predefined (human designed) library - these may be thought of as the leaf-level modules in the design hierarchy. Design re-use and increasing sophistication of module libraries inevitably leads to leaf modules becoming larger and more complex. As these modules are, by definition, atomic, a synthesis system is unable to capitalise on any internal similarities the leaf modules may possess. This paper describes the design, construction and effects of using a hierarchically defined module library. The set of leaf-level modules made available to the synthesis environment is conventional - add, subtract, multiply and so on - but the optimiser is capable of ?ripping apart? these modules to manipulate their inner structures. Two advantages accrue from this technique: (1) it is possible to optimise behavioural designs far more effectively, with up to a 65% reduction in area, and a 46% reduction in delay reported, and (2) it is possible to build library modules that have tightly controllable internal timing relationships. This is essential when designing systems that communicate externally via low-level protocols, but behavioural synthesis, by its very nature, usually distorts timing information. Using this technique, it is possible to create ?islands of fixed timing? embedded in the synthesised design.

[1]  Zebo Peng.  Synthesis of VLSI Systems with the CAMAD Design Aid , 1986, DAC 1986.

[2]  Mark Zwolinski,et al.  Simultaneous optimisation of dynamic power, area and delay in behavioural synthesis , 2000 .

[3]  Alice C. Parker,et al.  MAHA: A Program for Datapath Synthesis , 1986, 23rd ACM/IEEE Design Automation Conference.

[4]  Andrew D. Brown,et al.  A VHDL Behavioural Synthesis System with Floating Point Support , 2000 .

[5]  A. D. Brown,et al.  Source level optimisation of VHDL for behavioural synthesis , 1997 .

[6]  Andrew D. Brown,et al.  On-line testing of statically and dynamically scheduled synthesized systems , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Mark Zwolinski,et al.  In-line test of synthesised systems exploiting latency analysis , 2000 .

[8]  Alice C. Parker,et al.  Sehwa: a software package for synthesis of pipelines from behavioral specifications , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Ron Miller,et al.  Scheduling using behavioral templates , 1995, DAC '95.

[10]  Pierre G. Paulin,et al.  Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Nikil D. Dutt,et al.  1995 high level synthesis design repository , 1995 .

[12]  K. G. Nichols,et al.  Multiple objective optimisation in a behavioural synthesis system , 1993 .

[13]  Andreas Münzner.  BADGE - A synthesis tool for customized arithmetic building blocks , 1992, Synthesis for Control Dominated Circuits.

[14]  Keith Richard Baker.  Multiple objective optimisation of data and control paths in a behavioural silicon compiler , 1992 .

[15]  Wayne H. Wolf,et al.  An Object-Oriented, Procedural Database for VLSI Chip Planning , 1986, 23rd ACM/IEEE Design Automation Conference.

[16]  Zebo Peng.  Synthesis of VLSI Systems with the CAMAD Design Aid , 1986, 23rd ACM/IEEE Design Automation Conference.

[17]  Alan C. Williams,et al.  A Behavioural VHDL Synthesis System using Data Path Optimisation , 1997 .

[18]  A. D. Brown,et al.  HDL-specific source level behavioural optimisation , 1997 .

[19]  Andrew D. Brown,et al.  Optimisation efficiency in behavioural synthesis , 1994 .