Arrangement for inner circuits of semiconductor memory device

PURPOSE: A semiconductor memory device is provided to reduce size and power dissipation. CONSTITUTION: Plural input buffers/shift blocks(211) are arranged adjacently while adjacently arranging plural output buffers/shift blocks(212). Thus, one clock line(261,262) is required for transferring each input/output control clock signal(sclk,tclk). Load on a delay synchronous loop circuit(241) driving the input/output control clock signals is decreased. Thus, the size of output drivers of the delay synchronous loop circuit is reduced. Accordingly, power dissipation and size of the delay synchronous loop circuit are decreased. In addition, the power dissipation and size of a Rambus DRAM(dynamic random access memory) semiconductor device(201) is decreased.