Cellular scan test generation for sequential circuits

The authors re-examine the concept of test machine embedding and present a new test machine architecture: cellular scan. Unlike the traditional scan machine architecture, the cellular scan machine requires no scan-out pin. A dynamic scan test generation algorithm, DYNASTEE, is introduced. It reduces test sequence length when compared to existing static test generation algorithms for scan architectures. It is shown that test sequence length can be minimized further by re-ordering the scan chain.<<ETX>>

[1]  James B. Angell,et al.  Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic , 1973, IEEE Transactions on Computers.

[2]  Ieee Circuits,et al.  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Jr. Clay Samuel Gloster.  Dynamic scan testing: a new paradigm , 1993 .

[4]  Srinivas Devadas,et al.  Test generation and verification for highly sequential circuits , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[6]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[7]  Klaus D. Müller-Glaser,et al.  On the selection of a partial scan path with respect to target faults , 1991, Proceedings of the European Conference on Design Automation..

[8]  Vishwani D. Agrawal,et al.  Finite state machine synthesis with embedded test function , 1990 .