Implementation of Low Power Parallel Compressor for Multiplier using Self Resetting Logic

In this paper a new approach of reducing power for a given system is developed that is self resetting logic, a parallel compressor is developed for multiplier by reducing its power with facilitation of this low power logic technique. By using this technique the power dissipation is significantly reduced with respect to other logics. By implementing the parallel compressor the performance of the circuit is increases.

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