Highly scalable effective work function engineering approach for multi-VT modulation of planar and FinFET-based RMG high-k last devices for (Sub-)22nm nodes

We report on a novel EWF engineering approach enabling wide V_T modulation in aggressively scaled RMG-HKL planar and multi-gate FinFET-based devices with high aspect-ratio gate trenches. Key features include: 1) Al diffusion control from fill-metal (Co_xAl_y) through an ultra-thin TaN layer on HfO₂/TiN and fine-tuned TiN/ TaN thicknesses; 2) optimized TiN films for enhanced (NMOS) or inhibited (PMOS) Al diffusion through it. For a total TiN/TaN thickness of less than 2.5nm, low-V_T NMOS planar bulk devices with σ(V_T)~14mV at L_gate~30nm and A_VT~1.98mV.μm are obtained. By increasing the bi-layer thickness to ~4nm a ~130mV higher V_T is achieved with no J_G nor EOT impact, and with the use of PDA resulting in an attractive ~10× J_G reduction. >500mV ΔV_T in narrow fin, triple-gate FinFETs (W_Fin≥5nm) enable low-V_T NMOS with improved mobility and BTI, up to ~6.3× reduced noise, and J_G ~0.16/1.9A/cm² at 1V, 9Å EOT for V_Tlin=0.29/0.11V, respectively.