Study of leakage current mechanisms in ballistic deflection transistors

In this paper, the Ballistic Deflection Transistor (BDT) is reviewed for variations in performance of the device including leakage with respect to geometry modifications. Monte Carlo and Silvaco modeling tools are used to study current leakage mechanism in BDT. Low power selection criteria and theory behind position of deflector in the device are examined. Since ballistic conduction is not dissipative, power loss should be low. Leakage can be reduced by placing deflector at about 25% of its own length lower than the exact centre of the device. Current leakages that occurred during device operation are compared with each other and with the output current. It is observed that magnitude of leakage current is distinct at different ports of the device. For a specific set of parameters, leakage is comparable to the output which essentially motivates to choose optimum device architecture.