Test scheduling optimization for 3D network-on-chip based on cloud evolutionary algorithm of Pareto multi-objective

In this paper, we present a parallel test strategy for bandwidth division multiplexing under the test access mechanism bandwidth constraint. The Pareto solution set is combined with a cloud evolutionary algorithm to optimize the test time and power consumption of a three-dimensional network-on-chip (3D NoC). In the proposed method, all individuals in the population are sorted in non-dominated order and allocated to the corresponding level. Individuals with extreme and similar characteristics are then removed. To increase the diversity of the population and prevent the algorithm from becoming stuck around local optima, a competition strategy is designed for the individuals. Finally, we adopt an elite reservation strategy and update the individuals according to the cloud model. Experimental results show that the proposed algorithm converges to the optimal Pareto solution set rapidly and accurately. This not only obtains the shortest test time, but also optimizes the power consumption of the 3D NoC.

[1]  Sungho Kang,et al.  NoC-Based SoC Test Scheduling Using Ant Colony Optimization , 2008 .

[2]  Midia Reshadi,et al.  Test Time Reduction in Automated Test Equipment (ATE)-Based Mechanism of Network-on-Chip Communication Infrastructure , 2015 .

[3]  Hong Wang,et al.  Accelerating Strategy for Functional Test of NoC Communication Fabric , 2010, 2010 19th IEEE Asian Test Symposium.

[4]  Luigi Carro,et al.  The impact of NoC reuse on the testing of core-based systems , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[5]  Li Hesong,et al.  Cloud model based algorithm for global optimization of functions , 2007 .

[6]  Luigi Carro,et al.  Power-aware noc reuse on the testing of core-based systems , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[7]  Zhang Guang.  An Evolutionary Algorithm Based on Cloud Model , 2008 .

[8]  Hong Xu,et al.  Unicast-Based Multicast Communication in Wormhole-Routed Networks , 1994, IEEE Trans. Parallel Distributed Syst..

[9]  Hannu Tenhunen,et al.  Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels , 2013, J. Comput. Syst. Sci..

[10]  Érika F. Cota,et al.  Constraint-Driven Test Scheduling for NoC-Based Systems , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Lothar Thiele,et al.  Multiobjective evolutionary algorithms: a comparative case study and the strength Pareto approach , 1999, IEEE Trans. Evol. Comput..

[12]  Partha Pratim Pande,et al.  Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation , 2009, IEEE Transactions on Computers.

[13]  Lei Zhang,et al.  TSV Minimization for Circuit — Partitioned 3D SoC Test Wrapper Design , 2013, Journal of Computer Science and Technology.

[14]  Krishnendu Chakrabarty,et al.  Test-time optimization in NOC-based manycore SOCs using multicast routing , 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

[15]  Luigi Carro,et al.  Reusing an on-chip network for the test of core-based systems , 2004, TODE.

[16]  Liu Yu.  Atomized Feature in Cloud Based Evolutionary Algorithm , 2009 .