A flexible multiplier for media processing

In the last years multimedia processing applications have gained more and more importance in the field of mobile and hand-held devices, requiring dedicated hardware platforms characterized by high performance computation capabilities with reduced area occupation and low power consumption. 2D graphics and signal processing applications in general benefit from the usage of integer single-instruction-multiple-data (SIMD) functional units, while 3D graphics applications can be significantly accelerated employing single precision floating-point functional units. This paper presents a model and implementation of a versatile multiplier able to perform either double precision, (paired) single precision floating-point multiplications or 16-bit or 8-bit SIMD integer (vector) multiplications; it was implemented on an FPGA device and compared to other floating-point multipliers and similar devices, each capable of performing only a limited subset of the proposed design. The results show that all the functionalities provided by the set of the other considered devices can be performed by the proposed design with a minor area overhead penalty and still competitive performance; thus the proposed multiplier represents in particular a good candidate for usage in area-limited designs.

[1]  Chia-Lin Yang,et al.  Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions , 2000, IEEE Trans. Computers.

[2]  Comparing Fixed-and Floating-Point DSPs , 2004 .

[3]  Michael J. Schulte,et al.  Multiplier architectures for media processing , 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.

[4]  Theo Ungerer,et al.  Processor architecture - from dataflow to superscalar and beyond , 1999 .

[5]  Sergio Bampi,et al.  Design of very deep pipelined multipliers for FPGAs , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[6]  Charles Roth,et al.  A low-power, high-speed implementation of a PowerPC/sup TM/ microprocessor vector extension , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).

[7]  Marc Tremblay,et al.  VIS speeds new media processing , 1996, IEEE Micro.

[8]  Majid Ahmadi,et al.  A reconfigurable digital multiplier architecture , 2003, CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436).

[9]  Steve Leibson,et al.  Flexible architectures for engineering successful SOCs , 2004, Proceedings. 41st Design Automation Conference, 2004..

[10]  E.E. Swartzlander,et al.  A recursive fast multiplier , 1998, Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284).

[11]  Uri C. Weiser,et al.  MMX technology extension to the Intel architecture , 1996, IEEE Micro.