A low-power minimum distance 1D-search engine using hybrid digital/analog circuit techniques

This minimum distance 1D-search engine (MDSE) realizes a pattern-matching hardware accelerator for portable multimedia and intelligent processing systems. The chip executes highly parallel computation of L/sub 1/-norms between an input key and stored multiple reference records, and search of the minimum distance among them in 1 dimensional (1D) memories. According to architectural-level power estimation, the proposed MDSE improves the power reduction by orders of magnitude as compared to the conventional systems, as the number of records increases. Two novel circuits, such as merged memory logic (MML) and digital/analog mixed winner-take-all (DAM-WTA) circuit, have been implemented with 0.6 /spl mu/m CMOS technology. The simulation results of the 4bit-8word MDSE show that the power dissipation (=2.8 mW at 3 V) of the MML coincides with the estimated power within 43% error, and the worst-case delay of the DAM-WTA is less than 80 ns.

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