论文信息 - 0.95V Substrate Bias Generator for Leak Power Reduction of 0.5V Digital Logic Circuits - 字舞流文

0.95V Substrate Bias Generator for Leak Power Reduction of 0.5V Digital Logic Circuits

G. S. Kim | S. Y. Lee | C. H. Choi | J. B. Kim | S. H. Oh | N. T. Trung | S. W. Kim

[1] Seok Won Jung,et al. CMVP Verification of AES RTL Block Using SystemC , 2006 .