Essential Issues in Multiprocessor Systems

During the past several years, a great number of proposals have been made with the objective to increase supercomputer performance by an order of magnitude on the basis of a utilization of new computer architectures. The present paper is concerned with a suitable classification scheme for comparing these architectures. It is pointed out that there are basically four schools of thought as to the most important factor for an enhancement of computer performance. According to one school, the development of faster circuits will make it possible to retain present architectures, except, possibly, for a mechanism providing synchronization of parallel processes. A second school assigns priority to the optimization and vectorization of compilers, which will detect parallelism and help users to write better parallel programs. A third school believes in the predominant importance of new parallel algorithms, while the fourth school supports new models of computation. The merits of the four approaches are critically evaluated. 50 references.

[1]  Janak H. Patel,et al.  Shared Cache for Multiple-Stream Computer Systems , 1983, IEEE Transactions on Computers.

[2]  Leon Presser Multiprogramming Coordination , 1975, CSUR.

[3]  David A. Padua,et al.  High-Speed Multiprocessors and Compilation Techniques , 1980, IEEE Transactions on Computers.

[4]  Leonard Kleinrock,et al.  A contiuum of time-sharing scheduling algorithms , 1970, AFIPS '70 (Spring).

[5]  Paul Feautrier,et al.  A New Solution to Coherence Problems in Multicache Systems , 1978, IEEE Transactions on Computers.

[6]  David W. Anderson,et al.  The IBM System/360 model 91: machine philosophy and instruction-handling , 1967 .

[7]  Jack B. Dennis,et al.  Data Flow Supercomputers , 1980, Computer.

[8]  Arvind,et al.  A critique of multiprocessing von Neumann style , 1983, ISCA '83.

[9]  Bruce D. Shriver,et al.  Local Microcode Compaction Techniques , 1980, CSUR.

[10]  Edward M. Riseman,et al.  Percolation of Code to Enhance Parallel Dispatching and Execution , 1972, IEEE Transactions on Computers.

[11]  Richard M. Russell,et al.  The CRAY-1 computer system , 1978, CACM.

[12]  Jack B. Dennis,et al.  First version of a data flow procedure language , 1974, Symposium on Programming.

[13]  Duncan H. Lawrie,et al.  The Prime Memory System for Array Access , 1982, IEEE Transactions on Computers.

[14]  Klaus J. Berkling,et al.  A Computing Machine Based on Tree Structures , 1971, IEEE Transactions on Computers.

[15]  Andrew R. Pleszkun,et al.  Structured Memory Access Architecture , 1983, ICPP.

[16]  C. A. R. Hoare,et al.  Communicating sequential processes , 1978, CACM.

[17]  Ian Watson,et al.  The Manchester prototype dataflow computer , 1985, CACM.

[18]  A. Gottleib,et al.  The nyu ultracomputer- designing a mimd shared memory parallel computer , 1983 .

[19]  Gururaj S. Rao,et al.  Performance Analysis of Cache Memories , 1978, JACM.

[20]  John W. Backus,et al.  Can programming be liberated from the von Neumann style?: a functional style and its algebra of programs , 1978, CACM.

[21]  GottliebAllan,et al.  Basic Techniques for the Efficient Coordination of Very Large Numbers of Cooperating Sequential Processors , 1983 .

[22]  Richard P. Hopkins,et al.  Data-Driven and Demand-Driven Computer Architecture , 1982, CSUR.

[23]  Arvind,et al.  Tagged token dataflow architecture , 1983 .

[24]  Kai Hwang,et al.  Computer architecture and parallel processing , 1984, McGraw-Hill Series in computer organization and architecture.

[25]  Michael Wolfe,et al.  The KAP/S-1 : An Advanced Source-to-Source Vectorizer for the S-1 Mark IIa Supercomputer , 1986, ICPP.

[26]  Alan Weiss,et al.  Allocating Independent Subtasks on Parallel Processors , 1985, IEEE Transactions on Software Engineering.

[27]  Pen-Chung Yew,et al.  A Synchronization Scheme and Its Applications for Large Multiprocessor Systems , 1984, ICDCS.

[28]  David A. Padua,et al.  A Second Opinion on Data Flow Machines and Languages , 1982, Computer.

[29]  Edward G. Coffman,et al.  Computer scheduling methods and their countermeasures , 1968, AFIPS Spring Joint Computing Conference.

[30]  Ralph Grishman,et al.  The NYU Ultracomputer—Designing an MIMD Shared Memory Parallel Computer , 1983, IEEE Transactions on Computers.

[31]  Charles L. Seitz,et al.  The cosmic cube , 1985, CACM.

[32]  Marc Snir,et al.  The Performance of Multistage Interconnection Networks for Multiprocessors , 1983, IEEE Transactions on Computers.

[33]  Pen-Chung Yew,et al.  SIMULATIONS AND ANALYSIS FOR A MULTIPROCESSOR SYSTEM WITH MULTIPROGRAMMING. , 1984 .

[34]  Daniel M. Dias,et al.  Analysis and Simulation of Buffered Delta Networks , 1981, IEEE Transactions on Computers.

[35]  Gregory R. Andrews,et al.  Concepts and Notations for Concurrent Programming , 1983, CSUR.

[36]  Kenneth E. Iverson,et al.  A Formal Description of SYSTEM/360 , 1964, IBM Syst. J..

[37]  Joseph A. Fisher,et al.  Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.

[38]  Burton J. Smith Architecture And Applications Of The HEP Multiprocessor Computer System , 1982, Optics & Photonics.

[39]  John L. Larson Multitasking on the Cray X-MP-2 Multiprocessor , 1984, Computer.

[40]  James C. Browne TRAC: An Environment for Parallel Computing , 1984, COMPCON.

[41]  H. T. Kung Why systolic architectures? , 1982, Computer.