HPRA: A pro-active Hotspot-Preventive high-performance routing algorithm for Networks-on-Chips

The inherent spatio-temporal unevenness of traffic flows in Networks-on-Chips (NoCs) can cause unforeseen, and in cases, severe forms of congestion, known as hotspots. Hotspots reduce the NoC's effective throughput, where in the worst case scenario, the entire network can be brought to an unrecoverable halt as a hotspot(s) spreads across the topology. To alleviate this problematic phenomenon several adaptive routing algorithms employ online load-balancing functions, aiming to reduce the possibility of hotspots arising. Most, however, work passively, merely distributing traffic as evenly as possible among alternative network paths, and they cannot guarantee the absence of network congestion as their reactive capability in reducing hotspot formation(s) is limited. In this paper we present a new pro-active Hotspot-Preventive Routing Algorithm (HPRA) which uses the advance knowledge gained from network-embedded Artificial Neural Network-based (ANN) hotspot predictors to guide packet routing across the network in an effort to mitigate any unforeseen near-future occurrences of hotspots. These ANNs are trained offline and during multicore operation they gather online buffer utilization data to predict about-to-be-formed hotspots, promptly informing the HPRA routing algorithm to take appropriate action in preventing hotspot formation(s). Evaluation results across two synthetic traffic patterns, and traffic benchmarks gathered from a chip multiprocessor architecture, show that HPRA can reduce network latency and improve network throughput up to 81% when compared against several existing state-of-the-art congestion-aware routing functions. Hardware synthesis results demonstrate the efficacy of the HPRA mechanism.

[1]  Hamid Sarbazi-Azad,et al.  An analytical model of fully-adaptive wormhole-routed k-ary n-cubes in the presence of hot spot traffic , 2000, Proceedings 14th International Parallel and Distributed Processing Symposium. IPDPS 2000.

[2]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[3]  Theocharis Theocharides,et al.  Intelligent Hotspot Prediction for Network-on-Chip-Based Multicore Systems , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Aaron Smith,et al.  Compiling for EDGE architectures , 2006, International Symposium on Code Generation and Optimization (CGO'06).

[5]  Saurabh Dighe,et al.  A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling , 2011, IEEE Journal of Solid-State Circuits.

[6]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[7]  José Duato,et al.  A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks , 1993, IEEE Trans. Parallel Distributed Syst..

[8]  L. Benini,et al.  Xpipes: a network-on-chip architecture for gigascale systems-on-chip , 2004, IEEE Circuits and Systems Magazine.

[9]  Natalie D. Enright Jerger,et al.  Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Masoud Daneshtalab,et al.  NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm , 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).

[11]  Derek L. Eager,et al.  A Novel Strategy for Controlling Hot Spot Congestion , 1989, ICPP.

[12]  José Duato,et al.  A new scalable and cost-effective congestion management strategy for lossless multistage interconnection networks , 2005, 11th International Symposium on High-Performance Computer Architecture.

[13]  Natalie D. Enright Jerger,et al.  DBAR: An efficient routing algorithm to support multiple concurrent applications in networks-on-chip , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

[14]  Axel Jantsch,et al.  Load distribution with the proximity congestion awareness in a network on chip , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[15]  Doug Burger,et al.  Implementation and Evaluation of On-Chip Network Architectures , 2006, 2006 International Conference on Computer Design.

[16]  Stephen W. Keckler,et al.  Regional congestion awareness for load balance in networks-on-chip , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[17]  Ming Li,et al.  DyXY - a proximity congestion-aware deadlock-free dynamic routing method for network on chip , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[18]  Hamid Sarbazi-Azad,et al.  Analytical Modeling of Wormhole-Routed k-Ary n-Cubes in the Presence of Hot-Spot Traffic , 2001, IEEE Trans. Computers.

[19]  Ran Ginosar,et al.  Access Regulation to Hot-Modules in Wormhole NoCs , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[20]  MarculescuRadu,et al.  Outstanding research problems in NoC design , 2009 .

[21]  Pedro López,et al.  A family of mechanisms for congestion control in wormhole networks , 2005, IEEE Transactions on Parallel and Distributed Systems.

[22]  Bill Lin,et al.  Destination-based adaptive routing on 2D mesh networks , 2010, 2010 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS).

[23]  Simha Sethumadhavan,et al.  Distributed Microarchitectural Protocols in the TRIPS Prototype Processor , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[24]  William J. Dally,et al.  A delay model and speculative architecture for pipelined routers , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[25]  Radu Marculescu,et al.  Analysis and optimization of prediction-based flow control in networks-on-chip , 2008, TODE.

[26]  Masoud Daneshtalab,et al.  BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs , 2008, 2008 Design, Automation and Test in Europe.

[27]  Bashir M. Al-Hashimi,et al.  Improving routing efficiency for network-on-chip through contention-aware input selection , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[28]  Akif Ali,et al.  Near-optimal worst-case throughput routing for two-dimensional mesh networks , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

[29]  Mithuna Thottethodi,et al.  Self-tuned congestion control for multiprocessor networks , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[30]  Radu Marculescu,et al.  DyAD - smart routing for networks-on-chip , 2004, Proceedings. 41st Design Automation Conference, 2004..

[31]  Kees G. W. Goossens,et al.  Congestion-Controlled Best-Effort Communication for Networks-on-Chip , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[32]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[33]  Masoud Daneshtalab,et al.  BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs to Avoid Congestion , 2008 .

[34]  Anil K. Jain,et al.  Artificial Neural Networks: A Tutorial , 1996, Computer.