Rapid design of discrete orthonormal wavelet transforms

A methodology which allows a non specialist to rapidly design silicon wavelet transform cores has been developed. This methodology is based on a generic architecture utilising time interleaved coefficients for the wavelet transform filters. The architecture is scaleable and it has been parameterised in terms of wavelet family, wavelet type, data word length and coefficient word length. The control circuit is designed in such a way that the cores can also be cascaded without any interface glue logic for any desired level of decomposition. This parameterisation allows the use of any orthonormal wavelet family, thereby extending the design space for improved transformation from algorithm to silicon. Case studies for stand alone and cascaded silicon cores for single and multi stage analysis respectively are reported. The typical design time to produce silicon layout of a wavelet based system has been reduced by an order of magnitude. The cores are comparable in area and performance to hand crafted designs. The designs have been captured in VHDL so they are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

[1]  V. Verma,et al.  A VHDL based functional compiler for optimum architecture generation of FIR filters , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[2]  J. Isoaho,et al.  Specification, hardware implementation and prototyping environment for image processing algorithms , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[3]  Mary Jane Irwin,et al.  VLSI architectures for the discrete wavelet transform , 1995 .

[4]  Roger F. Woods,et al.  Architectural Synthesis of Digital Signal Processing Algorithms Using “IRIS” , 1997, J. VLSI Signal Process..

[5]  Gauthier Lafruit,et al.  Implementation aspects of FIR filtering in a Wavelet Compression Scheme , 1996 .

[6]  D. Trainor,et al.  Rapid design of complex DSP cores , 1997, Proceedings of the 23rd European Solid-State Circuits Conference.

[7]  Andreas Klappenecker,et al.  Methods for regular VLSI implementations of wavelet filters , 1996, Optics & Photonics.

[8]  Harold H. Szu,et al.  Fast algo-tectures for discrete wavelet transforms , 1996, Defense + Commercial Sensing.

[9]  Olivier Rioul,et al.  Fast algorithms for discrete and continuous wavelet transforms , 1992, IEEE Trans. Inf. Theory.

[10]  John V. McCanny,et al.  Hierarchical VHDL libraries for DSP ASIC design , 1997, 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[11]  Chaitali Chakrabarti,et al.  Architectures for wavelet transforms: A survey , 1996, J. VLSI Signal Process..

[12]  S. Molloy,et al.  A video codec chipset for wireless multimedia networking , 1995, VLSI Signal Processing, VIII.

[13]  Stephen W. Kercel,et al.  Hardware implementation of multiresolution filtering for broadband instrumentation , 1995, Defense, Security, and Sensing.

[14]  A. S. Lewis,et al.  VLSI architecture for 2-D Daubechies wavelet transform without multipliers , 1991 .