FPGAs BIST Evaluation

This paper addresses the problem of Test Effectiveness (TE) evaluation of digital circuits implemented in FPGAs. A Hardware Fault Simulation (HFS) technique, particularly useful for evaluating the effectiveness of built-in self-test (BIST) is detailed. This HFS, efficiently, injects and un-injects faults using small partial reconfiguration files and ascertain (or not) the BIST to be used in the FPGA circuits. Different fault models are compared regarding their efficiency and complexity. The methodology is fully automated for Xilinx Spartan and Virtex FPGAs. Results, using a Digilab2 board, ISCAS’85 and 89 benchmarks, show that our methodology can be accurate and orders of magnitude faster than software fault simulation even with more demanding fault models.

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