Space Use-Case: Onboard Satellite Image Classification

[1]  Andrew D. Back,et al.  A spiking neural network architecture for nonlinear function approximation , 2001, Neural Networks.

[2]  Jimmy Ba,et al.  Adam: A Method for Stochastic Optimization , 2014, ICLR.

[3]  Ricardo Tapiador-Morales,et al.  Neuromorphic LIF Row-by-Row Multiconvolution Processor for FPGA , 2019, IEEE Transactions on Biomedical Circuits and Systems.

[4]  M.H. Hassoun,et al.  Fundamentals of Artificial Neural Networks , 1996, Proceedings of the IEEE.

[5]  Yurong Liu,et al.  A survey of deep neural network architectures and their applications , 2017, Neurocomputing.

[6]  Andrew S. Cassidy,et al.  Conversion of artificial recurrent neural networks to spiking neural networks for low-power neuromorphic hardware , 2016, 2016 IEEE International Conference on Rebooting Computing (ICRC).

[7]  Benoît Miramond,et al.  Confronting machine-learning with neuroscience for neuromorphic architectures design , 2018, 2018 International Joint Conference on Neural Networks (IJCNN).

[8]  Sébastien Bilavarn,et al.  An FPGA-Based Hybrid Neural Network Accelerator for Embedded Satellite Image Classification , 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS).

[9]  WangYu,et al.  [DL] A Survey of FPGA-based Neural Network Inference Accelerators , 2019 .

[10]  Yoshua Bengio,et al.  Gradient-based learning applied to document recognition , 1998, Proc. IEEE.

[11]  Tobias Delbrück,et al.  Frame-free dynamic digital vision , 2008 .

[12]  Fabien Marty,et al.  TULIPP: Towards ubiquitous low-power image processing platforms , 2016, 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS).

[13]  Benoit Miramond,et al.  Information Coding and Hardware Architecture of Spiking Neural Networks , 2019, 2019 22nd Euromicro Conference on Digital System Design (DSD).

[14]  Angel Jiménez-Fernandez,et al.  On the AER convolution processors for FPGA , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[15]  David Heckerman,et al.  Models and Selection Criteria for Regression and Classification , 1997, UAI.

[16]  Geoffrey E. Hinton,et al.  Rectified Linear Units Improve Restricted Boltzmann Machines , 2010, ICML.

[17]  Shih-Chii Liu,et al.  Conversion of Continuous-Valued Deep Networks to Efficient Event-Driven Networks for Image Classification , 2017, Front. Neurosci..

[18]  Eugene M. Izhikevich,et al.  Simple model of spiking neurons , 2003, IEEE Trans. Neural Networks.

[19]  Alejandro Linares-Barranco,et al.  Test Infrastructure for Address-Event-Representation Communications , 2005, IWANN.

[20]  Ananya Muddukrishna,et al.  Supporting Utilities for Heterogeneous Embedded Image Processing Platforms (STHEM): An Overview , 2018, ARC.

[21]  Geoffrey E. Hinton,et al.  Learning internal representations by error propagation , 1986 .

[22]  Lloyd W. Massengill,et al.  Basic mechanisms and modeling of single-event upset in digital microelectronics , 2003 .

[23]  Matthew W. Pennell,et al.  Prioritizing phylogenetic diversity captures functional diversity unreliably , 2018, Nature Communications.

[24]  Yoshua Bengio,et al.  BinaryConnect: Training Deep Neural Networks with binary weights during propagations , 2015, NIPS.

[25]  Christof Koch,et al.  Generalized leaky integrate-and-fire models classify multiple neuron types , 2017, Nature Communications.

[26]  Sven Behnke,et al.  Evaluation of Pooling Operations in Convolutional Architectures for Object Recognition , 2010, ICANN.

[27]  Weizheng Wang,et al.  Development of convolutional neural network and its application in image classification: a survey , 2019, Optical Engineering.

[28]  Daniel Svozil,et al.  Introduction to multi-layer feed-forward neural networks , 1997 .