Modeling flexible Networks On-Chip

The Multi-Processors Systems on a chip (MPSoC) era is bringing about many new challenges for systems design in terms of computation and communication subsystems complexity. Interconnection systems became a pivotal component of the overall design, providing designers with advanced communication features such a split transactions, atomic operations and security adds-on. Momentum is building behind Networks on-chip (NoC) as future on-chip interconnection technology. Networks on-chip role isabout to take over shared busses whose scalability properties are already a major bottleneck for system design. Modeling of on-chip network is an exacting work; networks models must be fast, accurate and they have to sport standard interfaces. The main contributions of this work to networks on-chip design and implementation are: (1) the development of a brand new, full-edged network on-chip simulator based on OCCN, an open-source framework for NoC modeling developed within sourceforge available at http://occn.sourceforge.net, (2) the successfull integration of heterogeneous simulation environments in extremely complex platforms used to benchmark real STMicroelectronics SoC and (3) a thorough understanding and contribution to the design of STNoC—, the new interconnection technology developed within AST Grenoble lab of STMicroelectronics for future generation systems. The modeling environment has been used to benchmark two STMicroelectronics systems on-chip for High Definition digital Television (HDTV).