X-Press Compactor for 1000x Reduction of Test Data

The paper presents a two-stage test response compactor with an overdrive section and scan chain selection logic. The proposed solution is capable of handling a wide range of X state profiles, offers compaction much higher than the ratio of scan chains to compactor outputs, and provides excellent diagnostic resolution

[1]  Minesh B. Amin,et al.  X-tolerant compression and application of scan-atpg patterns in a bist architecture , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[2]  Subhasish Mitra,et al.  X-compact: an efficient response compaction technique , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Bernd Becker,et al.  X-masking during logic BIST and its impact on defect coverage , 2006, IEEE Trans. Very Large Scale Integr. Syst..

[4]  Hideo Fujiwara,et al.  Design and analysis of multiple weight linear compactors of responses containing unknown values , 2005, IEEE International Conference on Test, 2005..

[5]  Leendert M. Huisman,et al.  Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[6]  Erik H. Volkerink,et al.  Response compaction with any number of unknowns using a new LFSR architecture , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[7]  Janusz Rajski,et al.  Modular compactor of test responses , 2006, 24th IEEE VLSI Test Symposium.

[8]  Vivek Chickermane,et al.  Channel masking synthesis for efficient on-chip test compression , 2004, 2004 International Conferce on Test.

[9]  Irith Pomeranz,et al.  On-chip compression of output responses with unknown values using lfsr reseeding , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[10]  Irith Pomeranz,et al.  On efficient X-handling using a selective compaction scheme to achieve high test response compaction ratios , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[11]  Alex Orailoglu,et al.  Test volume and application time reduction through scan chain concealment , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[12]  Steven S. Lumetta,et al.  X-tolerant signature analysis , 2004 .

[13]  Irith Pomeranz,et al.  On Compacting Test Response Data Containing Unknown Values , 2003, ICCAD 2003.

[14]  Brion L. Keller,et al.  OPMISR: the foundation for compressed ATPG vectors , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[15]  Janak H. Patel,et al.  Application of Saluja-Karpovsky compactors to test responses with many unknowns , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[16]  Nilanjan Mukherjee,et al.  Embedded deterministic test , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Brion L. Keller,et al.  Extending OPMISR beyond 10x Scan Test Efficiency , 2002, IEEE Des. Test Comput..

[18]  Janusz Rajski,et al.  Compactor independent direct diagnosis , 2004, 13th Asian Test Symposium.

[19]  Sudhakar M. Reddy,et al.  On methods to improve location based logic diagnosis , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[20]  Wu-Tung Cheng,et al.  X-filter: filtering unknowns from compacted test responses , 2005, IEEE International Conference on Test, 2005..

[21]  Sudhakar M. Reddy,et al.  Convolutional compaction of test responses , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[22]  Irith Pomeranz,et al.  On output response compression in the presence of unknown output values , 2002, DAC '02.

[23]  Nilanjan Mukherjee,et al.  Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.