FPGA implementation of Reed-Solomon codes

Reed--Solomon (RS) codes are non-binary cyclic error correcting codes. They are block-based error correcting codes with a wide range of applications in digital communications and storage and are used in various applications that required robust and energy efficient transmissions. The proposed project model is FPGA implementation and performance analysis of the RS (n, k) codec architecture. The proposed model is to design RS codec to occupy the least amount of logic blocks, be fast and parameterizable. In the proposed model both encoder and decoder will be synthesized to other FPGA architectures.