UNION: A unified inter/intra-chip optical network for chip multiprocessors

As modern computing systems become increasingly complex, communication efficiency among and inside chips has become as important as the computation speeds of individual processor cores. Traditionally, inter-chip and intra-chip communication architectures are separately designed to maximize design flexibility under different constraints. However, jointly designing communication architectures for both inter-chip and intra-chip communication could potentially yield better solutions. In this paper, we present a unified inter/intra-chip optical network, called UNION, for chip multiprocessors (CMP). UNION is based on recent progress in nano-photonic technologies. It connects not only processors on a single CMP but also multiple CMPs in a system. UNION employs a hierarchical optical network to separate inter-chip communication traffic from intra-chip communication traffic. It fully utilizes a single optical network to transmit both payload packets and control packets. The network controller on each CMP not only manages intra-chip communications but also collaborate with each other to facilitate inter-chip communications. We compared CMPs using UNION with those using a matched electronic counterpart in 45 nm process. Based on eight applications, simulation results show that on average UNION improves CMP performance by 3.1X while reducing 92% of network energy consumption and 52% of communication delay.

[1]  F. Ellinger,et al.  A 100-mW 4/spl times/10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects , 2005, IEEE Journal of Solid-State Circuits.

[2]  Reduction methods for adapting optical network on chip topologies to specific routing applications , 2007 .

[3]  Pedro López,et al.  Deterministic versus Adaptive Routing in Fat-Trees , 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

[4]  C. Berger,et al.  Characterization of parallel optical-interconnect waveguides integrated on a printed circuit board , 2004, SPIE Photonics Europe.

[5]  F. Ellinger,et al.  A 100mW 4/spl times/10Gb/s transceiver in 80nm CMOS for high-density optical interconnects , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[6]  Luca P. Carloni,et al.  Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors , 2008, IEEE Transactions on Computers.

[7]  Jung Ho Ahn,et al.  Corona: System Implications of Emerging Nanophotonic Technology , 2008, 2008 International Symposium on Computer Architecture.

[8]  H. Thienpont,et al.  MT-compatible laser-ablated interconnections for optical printed circuit boards , 2004, Journal of Lightwave Technology.

[9]  Jörg Henkel,et al.  A design methodology for application-specific networks-on-chip , 2006, TECS.

[10]  Hyo-Hoon Park,et al.  Passively assembled optical interconnection system based on an optical printed-circuit board , 2006 .

[11]  Wei Zhang,et al.  A Hierarchical Hybrid Optical-Electronic Network-on-Chip , 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

[12]  G. Masini,et al.  A Four-Channel, 10 Gbps Monolithic Optical Receiver In 130nm CMOS With Integrated Ge Waveguide Photodetectors , 2007, OFC/NFOEC 2007 - 2007 Conference on Optical Fiber Communication and the National Fiber Optic Engineers Conference.

[13]  James E. Jaussi,et al.  A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[14]  A. Andreou,et al.  A 2.5-mW SOS CMOS optical receiver for chip-to-chip interconnect , 2004, Journal of Lightwave Technology.

[15]  C L Schow,et al.  Chip-to-chip board-level optical data buses , 2008, OFC/NFOEC 2008 - 2008 Conference on Optical Fiber Communication/National Fiber Optic Engineers Conference.

[16]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[17]  Christopher Batten,et al.  Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics , 2008, 2008 16th IEEE Symposium on High Performance Interconnects.

[18]  David H. Albonesi,et al.  Phastlane: a rapid transit optical routing network , 2009, ISCA '09.

[19]  Wei Zhang,et al.  A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[20]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[21]  Fang Xu,et al.  Cascaded active silicon microresonator array cross-connect circuits for WDM networks-on-chip , 2008, SPIE OPTO.

[22]  F. Xia,et al.  Ultracompact optical buffers on a silicon chip , 2007 .

[23]  M. Horowitz,et al.  A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS , 2007, IEEE Journal of Solid-State Circuits.

[24]  S. Xiao,et al.  Multiple-channel silicon micro-resonator based filters for WDM applications. , 2007, Optics express.

[25]  A Syrbu,et al.  10 Gbps VCSELs with High Single Mode Output in 1310nm and 1550 nm Wavelength Bands , 2008, OFC/NFOEC 2008 - 2008 Conference on Optical Fiber Communication/National Fiber Optic Engineers Conference.

[26]  Alyssa B. Apsel,et al.  Leveraging Optical Technology in Future Bus-based Chip Multiprocessors , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[27]  J. Doylend,et al.  Design and Simulation of an Integrated Fiber-to-Chip Coupler for Silicon-on-Insulator Waveguides , 2006, IEEE Journal of Selected Topics in Quantum Electronics.