The Effect of Cache on the Performance of a Multi-Threaded Pipelined RISC Processor

This paper examines the effects of multithreaded pipelining on the CPI (cycles per instruction) of a RISC processor. The desired CPI in a conventional (single-threaded) RISC processor is one instruction per cycle. However, the CPI is typically more than one because of data hazards, control hazards, and resource hazards in the pipeline. A multi-threaded processor performs a context switch between every instruction. Multi-threaded pipelining holds out the promise of achieving a lower CPI because it can eliminate data and control hazards, and mask the effects of memory latency. However, multi-threaded pipelining reduces cache hit ratios and requires more chip area to implement. In this paper, we present a model for predicting the CPI of a multithreaded pipelined processor. We also present the results of trace-driven simulations of single- and multi-threaded processors. These data show that, for reasonable implementation technologies, and taking into account the chip area penalty, a multi-threaded processor can achieve a lower CPI than a single-threaded processor.

[1]  Mark Horowitz,et al.  Architectural tradeoffs in the design of MIPS-X , 1987, ISCA '87.

[2]  Michael J. Flynn,et al.  And Now a Case for More Complex Instruction Sets , 1987, Computer.

[3]  Norman P. Jouppi,et al.  Organization and VLSI implementation of MIPS , 1984 .

[4]  M. Milenkovitch.  Operating systems -- concepts and design , 1987 .

[5]  Edward S. Davidson,et al.  A multiminiprocessor system implemented through pipelining , 1974, Computer.

[6]  Janusz S. Kowalik,et al.  Parallel MIMD computation : the HEP supercomputer and its applications , 1985 .

[7]  Terry A. Welch,et al.  A Technique for High-Performance Data Compression , 1984, Computer.

[8]  Mark Horowitz,et al.  An analytical cache model , 1989, TOCS.

[9]  Veljko Milutinović.  Tutorial on advanced microprocessors and high-level language computer architecture , 1986 .

[10]  Kentaro Shimizu,et al.  CPC (Cyclic Pipeline Computer) - An Architecture Suited for Josephson and Pipelined-Memory Machines , 1989, IEEE Trans. Computers.

[11]  J. E. Thornton,et al.  Parallel operation in the control data 6600 , 1964, AFIPS '64 (Fall, part II).

[12]  Carlo H. Séquin,et al.  A VLSI RISC , 1982, Computer.

[13]  Peter Steenkiste,et al.  Lisp on a reduced-instruction-set processor: characterization and optimization , 1988, Computer.

[14]  Paul Chow.  MIPS-X instruction set and programmer''s manual , 1986 .

[15]  Robert H. Halstead,et al.  MASA: a multithreaded processor architecture for parallel symbolic computing , 1988, [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings.

[16]  Fred C. Chow,et al.  A portable machine-independent global optimizer--design and measurements , 1984 .

[17]  T.S. Perry.  Intel's secret is out , 1989, IEEE Spectrum.