Optimal temporal partitioning and synthesis for reconfigurable architectures
暂无分享,去创建一个
[1] Fred W. Glover,et al. Technical Note - Converting the 0-1 Polynomial Programming Problem to a 0-1 Linear Program , 1974, Oper. Res..
[2] Alice C. Parker,et al. CHOP: a constraint-driven system-level partitioner , 1991, 28th ACM/IEEE Design Automation Conference.
[3] Catherine H. Gebotys,et al. Optimal synthesis of multichip architectures , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.
[4] Catherine H. Gebotys,et al. An optimal methodology for synthesis of DSP multichip architectures , 1995, J. VLSI Signal Process..
[5] Fred W. Glover,et al. Further Reduction of Zero-One Polynomial Programming Problems to Zero-One linear Programming Problems , 1973, Oper. Res..
[6] Ranga Vemuri,et al. Resource constrained RTL partitioning for synthesis of multi-FPGA designs , 1997, Proceedings Tenth International Conference on VLSI Design.
[7] Catherine H. Gebotys,et al. Optimal VLSI Architectural Synthesis: Area, Performance and Testability , 1991 .
[8] Giovanni De Micheli,et al. Partitioning of functional models of synchronous digital systems , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[9] Peter Marwedel,et al. OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming , 1994, EURO-DAC '94.
[10] Peter Marwedel,et al. An Algorithm for Hardware/Software Partitioning Using Mixed Integer Linear Programming , 1997, Des. Autom. Embed. Syst..
[11] Chung-Ta King,et al. MULTIPAR: behavioral partitioning for synthesizing application-specific multiprocessor architecture , 1992, [1992] Proceedings The European Conference on Design Automation.
[12] Pierre Hansen,et al. Constrained Nonlinear 0-1 Programming , 1989 .
[13] Peter Marwedel,et al. Hardware/software partitioning using integer programming , 1996, Proceedings ED&TC European Design and Test Conference.