Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging

This paper presents modeling and simulation results of a modified copper-column-based flip-chip interconnect with ultrafine pitch for wafer-level packaging, and the process and prototyping procedure are described as well. This interconnect consists of multiple copper columns which are electrically in parallel and supporting a solder bump. A simple analytical model has been developed for correlation between the interconnect geometry and the thermal fatigue life. In comparison to the conventional single-copper-column (SCC) interconnects, numerical analysis reveals that the multi-copper-column (MCC) interconnect features enhanced compliances and, hence, higher thermomechanical reliability, while the associated electrical parasitics (R, L, and C) at dc and moderate frequencies are still kept low. Parametric studies reveal the effects of geometric parameters of MCC interconnects on both compliances and electrical parasitics, which in turn facilitate design optimization for best performance. By using coplanar waveguides (CPWs) as feed lines on both chip and package substrate, a high-frequency (up to 40 GHz) S-parameter analysis is conducted to investigate the transmission characteristics of the MCC interconnects within various scenarios which combines various interconnect pitches and common chip and package substrates. An equivalent lumped circuit model is proposed and the circuit parameters (R, L, C, and G) are obtained throughout a broad frequency range. Good agreement is achieved for the transmission characteristics between the equivalent lumped circuit model and direct simulation results.

[1]  Hai-Young Lee,et al.  Suppression of the CPW leakage in common millimeter-wave flip-chip structures , 1998 .

[2]  R. Vahldieck,et al.  S-parameter analysis of flip-chip transitions , 1995, Proceedings of Electrical Performance of Electronic Packaging.

[3]  Martin H. Graham,et al.  Book Review: High-Speed Digital Design: A Handbook of Black Magic by Howard W. Johnson and Martin Graham: (Prentice-Hall, 1993) , 1993, CARN.

[4]  M. B. Steer,et al.  Foundations of Interconnect and Microstrip Design: Edwards/Foundations of Interconnect and Microstrip Design , 2000 .

[5]  Herbert Reichl,et al.  Board level reliability of a waferlevel CSP using stacked solder spheres and a solder support structure (S/sup 3/) , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[6]  H. Shigesawa,et al.  New interesting leakage behavior on coplanar waveguides of finite and infinite widths , 1991, 1991 IEEE MTT-S International Microwave Symposium Digest.

[7]  Rao Tummala,et al.  Fundamentals of Microsystems Packaging , 2001 .

[8]  Michael B. Steer,et al.  Foundations of Interconnect and Microstrip Design , 2000 .

[9]  James D. Meindl,et al.  Electrical performance of compliant wafer level package , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[10]  H. Massler,et al.  Advantages of flip chip technology in millimeter-wave packaging , 1997, 1997 IEEE MTT-S International Microwave Symposium Digest.

[11]  W. Engelmaier.  Fatigue Life of Leadless Chip Carrier Solder Joints During Power Cycling , 1983 .

[12]  Mikio Tsuji,et al.  New surface-wave-like mode on CPWs of infinite width and its role in explaining the leakage cancellation effect , 1992, 1992 IEEE Microwave Symposium Digest MTT-S.

[13]  Qi Zhu,et al.  A Lithography-Based Compliant Chip-to-Substrate Wafer-Level Interconnect , 2002 .

[14]  Frederick Warren Grover,et al.  Inductance Calculations: Working Formulas and Tables , 1981 .

[15]  T. Kawahara.  SuperCSP/sup TM/ , 2000 .

[16]  Delin Li,et al.  A Wide Area Vertical Expansion (WAVE/sup TM/) packaging process development , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[17]  P. Garrou,et al.  Wafer level chip scale packaging (WL-CSP): an overview , 2000, ECTC 2000.

[18]  K. Seelig,et al.  The status of lead-free solder alloys , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[19]  E.H. Wong,et al.  Fatigue life estimation of a stretched-solder-column ultra-fine-pitch wafer level package using the macro-micro modelling approach , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).