An asynchronous, iterative implementation of the original Booth multiplication algorithm

One of the main reasons for using asynchronous design is that it offers the opportunity to exploit the data-dependent latency of many operations in order to achieve low-power, high-performance, or low area. This paper describes a novel, asynchronous, iterative multiplier which exhibits data-dependency in both the number of iterations required to produce the result and in the delay of each step of the iteration. The preliminary evaluation of the multiplier, implemented using standard-cells, shows that speed improvements can be achieved in comparison to a standard iterative, radix-4 Booth multiplier.

[1]  Neil W. Bergmann,et al.  ata Asynchronous Multipliers with ata Dependent Computation Times , 1997 .

[2]  Brian de Alwis,et al.  How to Achieve Worst-Case Performance , 2001 .

[3]  Peter A. Beerel,et al.  Speculative completion for the design of high-performance asynchronous dynamic adders , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[4]  Andrew D. Booth,et al.  A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .

[5]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[6]  Jim D. Garside.  A CMOS VLSI Implementation of an Asynchronous ALU , 1993, Asynchronous Design Methodologies.

[7]  Deog-Kyoon Jeong,et al.  A 32/spl times/32 self-timed multiplier with early completion , 1999, AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360).

[8]  Chris J. Myers,et al.  A standard-cell self-timed multiplier for energy and area critical synchronous systems , 2001, Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001.